For most of the past three years, the AI hardware supply chain has run through a single chokepoint: TSMC’s CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging lines. Every major AI accelerator, including Nvidia’s GPUs, Google’s Tensor Processing Units (TPUs), and Amazon’s Trainium chips, has depended on CoWoS to stitch compute dies to stacks of high-bandwidth memory.
That dependency is now being tested. In mid-2026, industry reports indicated that Google’s next-generation TPU would move away from CoWoS entirely, adopting Intel’s EMIB (Embedded Multi-Die Interconnect Bridge) packaging platform instead. Rather than treat the defection as a threat, TSMC chairman C.C. Wei responded by publicly welcoming Intel’s involvement in the packaging market, a response that only makes sense once TSMC’s broader packaging strategy, capacity math, and outsourcing relationships are laid out in full.
Google’s Next-Generation TPU Leaves CoWoS for Intel’s EMIB-T
According to a report from semiconductor research firm SemiAnalysis, Google’s ninth-generation TPU, internally codenamed “Humufish,” will adopt Intel’s EMIB-T packaging rather than TSMC’s CoWoS. EMIB-T is an enhanced variant of Intel’s existing EMIB architecture, and the appeal is structural: it is not constrained by the reticle-size limits that cap CoWoS package size, it eliminates the need for a costly silicon interposer, and it offers better power-delivery efficiency for large AI accelerator packages. Yield remains the open question, and analysts have asked whether Google’s later TPU generations could shift back to TSMC if Intel’s packaging yields disappoint at scale.
The context that makes this move plausible is TSMC’s own capacity squeeze: CoWoS lead times stretched to as long as 78 weeks in 2026, and the company’s lines have been effectively sold out through the year. Google is not acting alone. MediaTek has said its next-generation chip program will rely on Intel’s EMIB-T exclusively, and Qualcomm and Tesla have both been reported to be evaluating the technology as well, describing a broader second-sourcing trend among major chip designers trying to reduce dependence on a single packaging supplier. None of this has been confirmed directly by Google; the reporting originates with SemiAnalysis and has since been repeated across trade press including Tom’s Hardware and Wccftech.
C.C. Wei Welcomes Intel’s Packaging Push
At a TSMC earnings call in 2026, chairman C.C. Wei said the company’s own packaging capacity is now so tight that it is limiting customers’ growth, and that TSMC welcomes “additional flexibility in the market,” describing Intel’s packaging technology as looking “good.” The comment reads less like a concession than a hedge: TSMC’s core profit engine is wafer fabrication, not packaging, so if Intel or Amkor absorbs overflow demand, TSMC’s customers can still fabricate at TSMC and simply assemble elsewhere, protecting the business that matters most without TSMC having to fund the capital spending needed to eliminate the CoWoS shortage on its own.
TSMC’s Countermove: The “EMIB-like” Program
TSMC’s current packaging capability is already substantial by industry standards, which is what makes its next move notable. CoWoS capacity has scaled from roughly 35,000 wafers a month at the end of 2024 to about 75,000 by the end of 2025, with a target of 120,000-130,000 wafers a month by the end of 2026 and a further step up toward 170,000 wafers a month in 2027.
That build-out is backed by heavy capital spending: TSMC’s total 2026 capital budget of $52-56 billion allocates roughly 10-20% to advanced packaging alone, funding two flagship sites, the AP7 campus in Chiayi, planned across multiple phases and set to become TSMC’s largest advanced-packaging hub, and the AP8 campus in Tainan, a former display-panel plant repurposed specifically for CoWoS production, where a second fab is being added. Even at that scale, every wafer of capacity is already spoken for, with CoWoS lines sold out through 2026, which is the backdrop against which TSMC’s own “EMIB-like” program should be read.
A report that surfaced on July 31, 2026 revealed that TSMC is developing an advanced packaging technology under the internal code name “EMIB-like,” in partnership with a Taiwanese substrate manufacturer. Media reports have not agreed on the partner’s identity: some name Kinsus Interconnect Technology, others report Unimicron Technology, and TSMC has not officially confirmed either the program or its partner.
The technical idea mirrors Intel’s approach: a silicon bridge embedded directly into the packaging substrate provides localized, high-density interconnect between adjacent dies, rather than relying on a full silicon interposer. This differs from TSMC’s existing CoWoS-L, which uses a separate redistribution-layer interposer with embedded Local Silicon Interconnect bridges and requires two distinct assembly steps; “EMIB-like,” if it follows Intel’s model, would use a single attachment process instead, potentially lowering cost. News of the program moved markets immediately: TSMC’s U.S.-listed ADR jumped 7.64% the day the report broke, closing at $403.31, with Taiwanese substrate and packaging stocks rallying in sympathy.
Three Packaging Paths: CoWoS, CoWoP, and CoPoS
TSMC’s response to surging AI packaging demand no longer rests on a single roadmap; it now spans three distinct paths, each aimed at a different point on the cost, density, and timeline curve. CoWoS remains the mainstream workhorse and is fully booked through 2026; rather than being phased out, its lifecycle is being extended to support packages larger than 14 reticles, with up to 24 HBM5E memory stacks and roughly a 48-times leap in compute power by 2029. CoPoS, the most forward-looking of the three, replaces round wafers with square panels to increase utilization of very large packages, but technical bottlenecks related to panel warpage and uniformity have pushed its mass production to Q4 2030, roughly two years behind the original schedule. CoWoP (Chip-on-Wafer-on-PCB) is the outlier of the group: rather than a TSMC-owned roadmap, it is an Nvidia-led initiative developed together with ASE Group’s SPIL and PCB suppliers, using a high-density PCB motherboard in place of a conventional substrate to cut cost and simplify the structure between chip and board.
TSMC is participating in feasibility work alongside Nvidia and SPIL, with CoWoP reportedly targeted to debut on Nvidia’s Rubin GR150 platform around October 2026 as a lower-cost complement to CoWoS rather than a replacement for it.
All three sit on the horizontal, chip-and-memory-side-by-side axis; SoIC, TSMC’s 3D die-stacking technology for bonding logic dies vertically with minimal signal loss, is a separate, complementary layer under TSMC’s “3D Fabric” umbrella rather than a fourth competing path, and it already ships combined with CoWoS today. The table below summarizes how the three compare, including how each one relates to SoIC.
Together, the three paths describe a layered strategy for the industry: CoWoS for near-term volume, CoWoP as a customer-driven, lower-cost complement built outside TSMC’s own roadmap, and CoPoS for an eventual panel-scale future, with the “EMIB-like” program sitting alongside all three as TSMC’s own answer to customers tempted by Intel.
TSMC’s Market Share in Advanced Packaging
TSMC’s position in advanced chip packaging is closer to a monopoly than ordinary market leadership. By widely cited industry estimates, TSMC controls roughly 95% of the global advanced chip packaging market. Demand has grown accordingly: CoWoS wafer demand is forecast to climb from around 484,000 wafers in 2025 to nearly 678,000 in 2026, a roughly 40% increase, with total demand approaching 1 million wafers in 2026 versus about 370,000 in 2024. Even with outsourced OSAT capacity included, the CoWoS supply-demand gap is expected to remain around 10% at the end of 2026, down from roughly 20% earlier in the year. Nvidia alone is reported to account for approximately 60% of TSMC’s CoWoS output.
Because CoWoS is TSMC’s proprietary process rather than an industry standard, this “market share” functions more like structural ownership of the category than a contested competitive position; neither Samsung, Intel, nor OSAT players such as Amkor and ASE have meaningfully dented it despite a multi-year shortage. That concentration also gives TSMC an incentive for restraint: CoWoS wafers reportedly carry gross margins approaching 80%, so TSMC benefits from keeping the line tight even as it says it welcomes more industry capacity elsewhere.
TSMC and Amkor’s Partnership
In October 2024, TSMC and Amkor Technology, one of the world’s largest OSAT providers, announced a ten-year agreement to expand advanced packaging capability in Arizona. Under the deal, TSMC contracts turnkey advanced packaging and test services from Amkor’s planned facility in Peoria, Arizona, to support customers whose wafers are fabricated at TSMC’s nearby Phoenix fabs, with the two companies naming TSMC’s Integrated Fan-Out (InFO) process and CoWoS itself among the technologies to be deployed there. The physical proximity of TSMC’s front-end fab and Amkor’s back-end facility is meant to shorten product cycle times and answer U.S. customer demand for a fully domestic supply chain. In effect, Amkor functions as TSMC’s outsourced packaging arm on U.S. soil, extending CoWoS and InFO capacity without TSMC having to build its own back-end plant from scratch.
Intel and Amkor’s Partnership
Amkor’s relationship with Intel runs on a separate track centered on EMIB. According to industry reporting, Intel first outsourced its high-end EMIB packaging to Amkor’s Songdo K5 facility in South Korea, its first-ever move to hand off this process externally, before expanding the partnership to Amkor’s Portugal site and a new Arizona campus, aiming to build what Amkor describes as a “robust alternative source” for EMIB assembly. The goal is to scale EMIB output quickly enough to meet demand from customers including Google, MediaTek, Qualcomm, and Tesla. The structural symmetry is notable: both TSMC and Intel, direct rivals in advanced packaging, are now leaning on the same outsourced assembler to add capacity neither can build fast enough alone, making Amkor’s own capacity decisions a real factor in how quickly the industry-wide packaging bottleneck eases.
Conclusion
The 2026 packaging landscape is not simply a two-way contest between TSMC and Intel. It is a system in which a capacity-constrained incumbent coexists with a resurgent challenger and a shared outsourced assembler that benefits from overflow demand on both sides. Google’s reported move to Intel’s EMIB-T is a real stress test, both for Intel’s ability to deliver acceptable yields at scale and for how much customer defection TSMC will tolerate before responding with more than words. TSMC’s own “EMIB-like” program is that response, a hedge that lets it offer a lower-cost, Intel-style option without abandoning CoWoS or its longer-term CoPoS roadmap, even as Nvidia pursues its own lower-cost CoWoP path with ASE’s SPIL on the side. Whether Intel’s packaging business becomes a durable second source, or a single-generation experiment that reverts to TSMC once yield data comes in, should become clearer over the next few quarters as Google’s ninth-generation TPU moves from design into production.
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