TSMC, the world’s leading semiconductor foundry, held its 2026 North America Technology Symposium on April 22 (local time). Under the theme “Expanding AI with Leadership Silicon,” the company unveiled several industry-leading semiconductor processes and packaging technologies. The highlight of the event was the first-ever revelation of the A13 process technology, designed to meet the extreme computing demands of next-generation AI, high-performance computing (HPC), and mobile applications.

“At TSMC, we understand our customers are always looking ahead to their next innovation, and they come to us for a reliable stream of new silicon technologies, like A13, meticulously engineered to be ready for high-volume production right when their visionary new designs demand them,” said TSMC Chairman and CEO Dr. C.C. Wei.

Advanced Logic Technology: A13 and A12 Lead the Roadmap

Following the announcement of A14 in 2025, TSMC officially introduced the A13 process technology this year. A13 is not just an extension of technology but a breakthrough in performance and area utilization:

• Density Optimization: Compared to A14, A13 saves 6% in chip area.

• High Compatibility: Design rules are fully backward-compatible with A14, allowing customers to quickly upgrade existing designs to the latest nanosheet transistor technology.

• Production Timeline: A13 is expected to enter production in 2029.

Additionally, TSMC enhanced its A14 platform and previewed A12 technology. This process will utilize “Super Power Rail” technology for backside power delivery and is expected to enter production in 2029.

TSMC is also advancing its N2 platform with the introduction of N2U. Using design and technology co-optimization (DTCO), N2U achieves a 3-4% speed increase or an 8-10% power reduction compared to N2P, with a 2-3% increase in logic density. Leveraging the process maturity and high yield of the N2 platform, N2U serves as a balanced choice for AI, HPC, and mobile applications, with production expected to start in 2028.

3DFabric® Advanced Packaging: Moving Toward the “System-on-Wafer” Era

To support the demand for higher computing power and memory within a single package, TSMC continues to expand its CoWoS® technology to integrate more silicon:

• Ultra-Large CoWoS: The Company is now producing 5.5-reticle size CoWoS and planning for even larger versions. A 14-reticle size CoWoS, capable of integrating approximately 10 large compute dies and 20 HBM stacks, is slated for production in 2028. This will be followed by an expansion beyond 14 reticles in 2029.

• SoW-X Technology: 40-reticle size SoW-X System-on-Wafer technology is also expected in 2029.

• Co-Packaged Optics (CPO): The company’s Compact Universal Photonic Engine (TSMC-COUPE™) will reach a critical milestone, with a true CPO solution (COUPE on substrate) expected to begin production in 2026. By integrating the COUPE optical engine directly into the package, TSMC achieves 2X power efficiency and a 10X latency reduction compared to a pluggable version on the circuit board. The technology is featured in a 200Gbps micro-ring modulator, a highly compact and energy-efficient solution to move data between racks in data centers

• TSMC will also launch TSMC-SoIC® 3D chip stacking on its most advanced platforms. A14-to-A14 SoIC is expected in 2029, offering 1.8x the die-to-die I/O density of N2-to-N2 SoIC technology to support higher data-transfer bandwidth.

Diverse Portfolio: Automotive, Robotics, and Specialty Technologies

For the automotive and robotics sectors, TSMC announced N2A, the first automotive process technology using nanosheet transistors, with AEC-Q100 validation expected in 2028. Meanwhile, the previously planned N3A enters production this year (2026), with over 10 customer products already planned.

Compared to N3A, N2A offers a 15-20% speed increase at the same power level. TSMC is also providing “Automotive Design Enablement” kits within the N2P Process Design Kit (PDK), allowing customers to begin designs early before N2A is fully validated.

In specialty technologies, TSMC is the first to bring high-voltage technology to the FinFET generation in 2026 with the N16HV process, primarily supporting display driver applications. For smartphone display drivers, N16HV increases gate density by 41% and reduces power consumption by 35% compared to N28HV. For near-eye displays, it reduces die area by 40% and power by over 20%, enhancing the usability of AR/VR devices such as smart glasses.

A Commitment to Being the Most Reliable Partner

Chairman and CEO Dr. C.C. Wei emphasized that TSMC will continue to lead the industry in density, performance, and power efficiency. He stated: “TSMC’s advanced process technologies lead the industry in density, performance, and power efficiency, and we continually strive to make them even better for our customers’ future products, ensuring customers’ success as their most reliable technological partner.”

Headquartered in Hsinchu, Taiwan, TSMC operates across Asia, Europe, and North America. In 2025, the company provided 305 process technologies for 534 customers, producing 12,682 products. This North America Technology Symposium kicks off a series of global events where TSMC will continue to showcase its manufacturing and process innovation.

Subscribe now

The global memory market is undergoing a permanent “structural shift” that will see NAND Flash shortages worsen in 2027 compared to 2026, according to Wallace Kou, President of Silicon Motion.

Speaking at the groundbreaking ceremony for Silicon Motion’s new headquarters in Nangang on April 13, Kou warned that the explosive growth of AI inference and Edge AI applications has created a demand-supply gap so vast that prices for certain NAND products have already surged by 4 to 10 times between August 2025 and March 2026.

The Death of the Old Cycle

Kou emphasized that the memory industry cannot return to its previous dynamics. “Resource reallocation driven by AI infrastructure has triggered a structural shift,” Kou stated. While retail markets remain soft, memory module manufacturers are seeing record profits—some expected to grow 200% to 300% by 2026—as they pivot from traditional consumer electronics to supplying global giants like Google and Meta.

Kou explained that the shortage is fueled by two primary factors:

• Insatiable AI Appetite: A single Nvidia NVL72 cabinet requires 1.16 PB (Petabytes) of operational storage, a staggering requirement that exists entirely outside of traditional data storage needs.

• Stagnant Supply Growth: Major manufacturers (Samsung, SK Hynix, Micron) remain scarred by previous downturns and are extremely cautious with capital expenditures. Kou noted that adding just 10,000 wafers of DRAM 1C capacity now costs $10 billion, while high-bandwidth memory (HBM4/4E) production continues to cannibalize resources for standard NAND and DRAM.

2027: The “Worst Year” for Supply

While some hope for a recovery, Kou’s projections suggest the peak of the crisis is still ahead.

“The shortage in 2027 will be even more severe than in 2026,” Kou predicted. “We likely won’t see any relief until the second half of 2027 or 2028, when new fabrication plants from the big three finally come online. Even then, ‘relief’ does not mean the problem is solved.”

Edge AI and the “Arrogance” of Hardware Giants

The shortage is no longer confined to the cloud. As Generative AI integrates into smartphones, PCs, and wearables (Edge AI), the demand for eMMC and other storage products is skyrocketing.

Kou noted a shift in market power, observing that some major smartphone brands remained “arrogant” regarding inventory levels until late 2025, only to realize too late that the global supply landscape had fundamentally changed. Silicon Motion currently reports that purchase orders (POs) far exceed their available supply, forcing the company to engage in precision manufacturing and supply chain “triage.”

Protecting the Weakest Links

One of Kou’s primary concerns is the potential for “broken chains” in the automotive and industrial sectors.

“It is unacceptable for a vehicle worth over $100,000 to be unable to ship because it lacks a storage component worth a few dozen dollars,” Kou said. Silicon Motion is currently prioritizing supply for the automotive industry to prevent such bottlenecks.

Ultimately, Kou dismissed fears of an “AI bubble,” pointing to the concrete, exploding demand for data storage. While consumer hardware shipments may dip slightly due to high costs, the industry is racing to adapt to a new era where memory is the most precious commodity in the AI ecosystem.

Reference:

https://news.cnyes.com/news/id/6418402

https://finance.ettoday.net/news/3148377

https://wantrich.chinatimes.com/news/20260413900337-420501

If you are visiting Touch Taiwan this week, the shift in atmosphere is unmistakable. What was once an exhibition strictly dedicated to displays, panels, and XR devices has evolved into a showcase of industrial transformation.

For years, Taiwan’s display and panel sectors have weathered a prolonged downturn, squeezed by aggressive price competition from Chinese giants like TCL and BOE. Facing a fight for survival, many local firms have successfully pivoted, diversifying into high-margin niche products such as ChLCD e-paper and specialized applications such as in-vehicle infotainment to reclaim their competitive edge.

However, one trend is so obvious that one cannot easily ignore it. Panel-Level Packaging (PLP) emerged as a central theme of this year's show. The influx of equipment suppliers specializing in Fan-Out PLP and Co-Packaged Optics (CPO) underscores a growing demand from panel manufacturers currently pursuing these technological transitions.

Even Corning set up a booth for advanced packaging solutions.

While SEMICON Taiwan was once the sole stage for the semiconductor industry, a notable shift is occurring: materials and equipment suppliers are now flooding into Computex and Touch Taiwan.

This migration reflects a strategic land grab. Given the industry’s explosive success—marked by years of consistent double-digit growth in both revenue and profit—companies are eager to claim their share of the market. They are aggressively seeking inroads into the one sector where Taiwan maintains a truly dominant global position.

This shift was further evidenced by a series of technical forums and seminars focused on advanced semiconductor packaging. Key sessions delved into high-growth areas such as Co-Packaged Optics (CPO), Fan-Out Panel-Level Packaging (FO-PLP), and Through-Glass Via (TGV) technology.

Share

I have deep respect for companies successfully navigating transformation by diversifying into highly specialized niches. BenQ is a prime example; their expansion into industrial materials was on full display, featuring a range of critical semiconductor solutions.

Key highlights from their showcase included:

• UV Adhesives: Tailored for AI server systems and currently under validation by a major client.

• Lithography & Protection: Dry film photoresist and micro-contamination control films.

• Back-end Processes: Dicing UV tape and CMP wafer cleaning brush rollers.

These high-precision materials demonstrate a serious commitment to penetrating the semiconductor fabrication supply chain.

AUO also dedicated a section of its booth to showcase an innovative satellite glass antenna. According to AUO representatives, this Ku-band Phased Array Translucent Antenna is a flagship product currently undergoing testing and validation with automotive clients.

The technology is designed to be seamlessly integrated— ”sandwiched”—between two layers of specialized sunroof glass. This allows vehicles to maintain low-earth-orbit (LEO) satellite connectivity, ensuring “boundless” communication even in remote areas.

Ultimately, this year’s exhibition was a testament to the agility of Taiwan's tech ecosystem. Whether it is BenQ’s move into the fab supply chain or AUO’s leap into LEO satellite connectivity, the message is clear: in an era of cut-throat competition, diversification and relentless innovation are the ultimate competitive advantage.

Subscribe now

Tesla and SpaceX founder and CEO Elon Musk announced his ambitious Terafab plan over the weekend. He explained the motive for doing so very clearly: the existing semiconductor manufacturers are producing too slowly, since they cannot provide what he needs; he must build the chips himself, otherwise there will be no chips to fulfill his vision of building a galactic civilization.

This report breaks down the transcript of Elon Musk’s announcement regarding “Terafab,” a joint initiative involving SpaceX, xAI, and Tesla to revolutionize semiconductor production for a space-faring civilization. By looking at the “whole picture”—including the skepticism from established industry leaders and the specific technical “bets” Musk is making—we can gain insights into a strategy that seeks to treat industrial dependence on the existing semiconductor ecosystem itself as an engineering flaw.

1. Content Distribution: Space Vision vs. Semiconductor Production

The transcript is a blend of visionary futurism and industrial planning. While the “what” is semiconductors, the “why” is almost entirely focused on space.

• Space Visions (~60% of content): A significant portion of the speech is dedicated to the Kardashev scale, the Sun’s energy output, becoming a multi-planetary species, and the logistics of moving compute to orbit. This serves as the motivational framework for the project.

• Semiconductor & Industrial Production (~40% of content): This portion focuses on the “Terafab” facility in Austin, the recursive design loop, the limitations of current supply chains (TSMC, Samsung), and the specific types of chips being developed (Edge/Inference vs. Space-Optimized).

2. Details of the Terafab Project

The Terafab is described as a “joint effort” between Tesla, xAI, and SpaceX.

The “Austin Advanced Technology Fab”

• Vertical Integration: Musk claims this is the first facility in the world to house everything needed to build a chip in a single building:

  • Logic and Memory production.

  • Lithography mask creation.

  • Packaging and Testing.

• The Recursive Loop: The primary advantage cited is the “incredibly fast recursive loop.” By having mask-making and testing in the same building, they can design, build, test, and redesign a chip in a fraction of the time required by traditional distributed supply chains.

• New Physics: Musk mentions pushing the “limit of physics in compute” and trying “wild and crazy things” facilitated by this fast iteration.

Physical Scale & Giga Texas Context

While the transcript doesn’t list exact dimensions, Musk uses Giga Texas as a scale reference. Current industrial context for Giga Texas (March 2026) includes:

• Footprint: Over 10 million square feet of factory floor (nearly 1 mile long).

• Terafab Prototype: The “Advanced Technology Fab” mentioned in the announcement is being integrated into the Giga Texas North Campus expansion, which is adding ~5.2 million square feet.

• Full-Scale Terafab: Musk indicates the final version will be “out of context” for current industry, with projections suggesting a target of 100 million square feet—roughly 10 times the size of the current main Giga Texas building—requiring thousands of acres.

Chip Specialization

Two primary categories of chips will be produced:

1. Edge/Inference Chips: Optimized for high-volume production (1–10 billion units/year) for use in Tesla vehicles and, primarily, the Optimus humanoid robot.

2. Space-Optimized Chips: Designed for high-energy ions, photons, and electron buildup. These chips will be designed to run “hotter” to minimize radiator mass and are intended for the “terawatt of compute” planned for orbit.

3. Production Goals and Output

Musk’s goals operate at a scale several orders of magnitude beyond current global capacity.

Terafab Output vs. Existing Supply Chain

• Current Global Output: Musk estimates the current AI compute output at roughly 20 gigawatts per year.

• Terafab Goal: The target is 1 terawatt (1,000 gigawatts) of compute per year.

• Comparison: Musk states that the combined output of all existing fabs on Earth (Samsung, TSMC, Micron, etc.) accounts for only 2% of the project’s requirements.

• Supply Chain Stance: While expressing gratitude to our existing supply chain, he notes they are not “comfortable expanding” at the rate he requires, necessitating the construction of the Terafab.

4. Risks and Realism: The “Overpromise” Factor

Media outlets like Reuters and Bloomberg frequently point out Musk’s tendency for “Elon Time”—setting aggressive deadlines that are rarely met. The Terafab project faces several monumental risks:

Technical and Execution Risks

• The Physics of Lithography: Building a leading-edge fab (capable of 2nm or below) is arguably the most difficult engineering feat on Earth. TSMC and Samsung have spent decades and hundreds of billions of dollars to master this. Musk’s “single building” recursive loop ignores the extreme sensitivity of lithography to environmental vibrations and contaminants.

• Space Radiation: Musk mentions “high-energy ions,” but radiation-hardening chips while maintaining high performance is a trade-off that has historically resulted in space-grade chips being several generations behind terrestrial ones.

• Starship Dependency: The entire plan relies on Starship achieving a cadence and cost-per-ton that is currently unprecedented. If Starship development stalls, the “Space Compute” logic collapses.

Historical Examples of Elon Musk’s Overpromising

Critics often cite these instances to temper expectations for the Terafab:

• Full Self-Driving (FSD): Since 2016, Musk has predicted that Tesla cars would be fully autonomous “next year.” As of 2026, FSD remains a Level 2 supervisory system.

• The Cybertruck: Originally unveiled in 2019 with a $39,900 starting price and a 2021 launch date, it arrived years late, significantly more expensive, and with different specs.

• Solar Roof: Promoted in 2016 as a revolutionary product that would be cheaper than a normal roof plus electricity. Deployment has been minimal and fraught with installation issues.

• Hyperloop: While Musk published a “white paper,” the actual implementation has been relegated to the “Boring Company” tunnels in Las Vegas, which are far from the original 700mph vacuum tube vision.

  Comments from the Semiconductor Industry Experts in Taiwan

  Andrew Lu, senior semiconductor analyst (translated):

  Elon Musk has announced plans to invest heavily in advanced semiconductor manufacturing. By analyzing technology sourcing, capital expenditure requirements, operating cash flow, long equipment lead times, component shortages, yield learning curves, and Musk’s oft-cited “first principles” approach, we can anticipate the many challenges the company is likely to face.

  While the company excels in technological innovation, Musk now appears to be pursuing too many ventures at once, risking a situation where nothing is executed with true excellence. For example, Tesla’s electric vehicle business has declined for two consecutive years and may continue to do so this year due to a lack of new models. The mass production of Optimus keeps being delayed year after year. Cybercab is still at least four to five years away from reaching the scale of millions of units needed to make a meaningful contribution to revenue and profit. Meanwhile, projects such as a lunar workstation (which seems to have shifted focus from Mars to the Moon) and space-based data centers may also take several more years before taking shape.

  As for the proposed “TeraFab,” it is highly likely that the vision will be drawn first, followed by years of trial-and-error execution before any tangible results are realized.

  Ming-chi Kuo on 3 Reasons Behind Musk’s Decision (translated):

  First, geopolitics. Elon Musk has publicly expressed concerns about the heavy concentration of semiconductor capacity in Taiwan. Even by 2030, TSMC’s advanced process and packaging capacity in the U.S. will remain limited—especially in advanced packaging, which may account for only around 10% of global capacity. Kuo believes Musk is aware of this, which is why he remarked, “Then you still have to solve the memory and packaging problem.”

  Second, R&D support and production flexibility. Kuo expects Tesla to have strong growth potential, but for TSMC, Tesla is still considered a second-tier customer. As a result, Tesla receives less R&D support and production flexibility compared to top-tier clients such as Apple and Nvidia. This is one of the reasons Tesla has shifted some AI6 orders to Samsung. The ultimate solution to this constraint is owning its own chip fabrication capability.

  Finally, integration advantages. Kuo notes that Musk’s technologies and products often operate at the cutting edge. Having the ability to customize key design and manufacturing steps—including owning a wafer fab—would enable tighter integration of final outputs and maximize the benefits of vertical integration.

  Commercial Times report, quoting industry insiders (translated and summarized):

  Industry insiders say starting at the 2nm node makes building a “Terafab” extremely difficult, with little chance of replicating TSMC’s model in the near term. However, Tesla could gradually enter the sector through advanced packaging, supply chain integration, and partnerships with Samsung and Intel, potentially reshaping the global chip landscape over time.

  The main challenge lies not in building fabs, but in achieving high yields at advanced nodes. At 2nm, the transition from FinFET to GAAFET requires major upgrades across materials, equipment, and processes. With hundreds of manufacturing steps per wafer, even minor deviations can significantly reduce yields. This highlights that long-term expertise in process integration, defect tracking, and learning cycles—not just capital—defines competitiveness, forming TSMC’s key advantage.

  Equipment constraints further complicate matters. EUV lithography systems are scarce, expensive, and have long lead times. Additionally, the U.S. trails Asia in semiconductor talent, manufacturing experience, and supply chain maturity. As a result, Tesla’s effort to build an advanced ecosystem in Texas will face significant time and execution challenges.

United Daily: Tesla Starts Recruiting Top-Notch Chip Engineers in Taiwan (translated)

Elon Musk has launched Tesla’s “TeraFab” initiative, committing US$20–25 billion to build a 2nm semiconductor fab. The company is now recruiting senior talent in Taiwan, targeting experienced engineers from TSMC and other leading firms, sparking a new wave of competition for semiconductor talent.

Tesla is specifically hiring process integration engineers—key roles responsible for coordinating advanced chip development. These positions oversee the full lifecycle of logic SoC production, including new product introduction, yield improvement, process optimization, testing, reliability, and defect reduction. In practice, they function as the “brain” behind yield and manufacturing efficiency in a wafer fab.

The hiring criteria are highly selective, requiring over 10 years of experience in advanced process development, deep familiarity with technologies such as FinFET, GAAFET, and backside power delivery, and expertise across FEOL, MOL, and BEOL stages. Candidates must also balance trade-offs among power, performance, area, and reliability while working with external partners.

Industry observers say Tesla is targeting engineers with hands-on experience in advanced-node transitions. This suggests a hybrid strategy: building internal capabilities while collaborating with external foundries, gradually advancing toward vertical integration.

Judy's LinkedIn Profile

5. Planned Usage & Logic for Space Compute

The end goal is to shift the majority of civilizational compute into space for three primary reasons:

1. Power Constraints: Earth is “power constrained.” Space offers “always sunny” conditions with no atmospheric attenuation or day-night cycles.

2. Cost Efficiency: Musk predicts that within 2–3 years, the cost of deploying AI in space will be lower than on Earth. Space solar is cheaper because it doesn’t need heavy protective glass or framing against weather.

3. Scalability: Increasing power on Earth leads to “NIMBY” (Not In My Backyard) issues and rising costs, whereas space becomes cheaper and easier to scale as launch costs (via Starship) drop.

Key Metrics for Success

• 10 million tons to orbit per year (enabled by Starship).

• 1 terawatt of solar power generation in space.

• 1 terawatt of compute production per year.

Is There Anything Elon Musk Knows but We Don’t?

Musk’s “secret” or “edge” isn’t necessarily a hidden scientific discovery, but rather a radical shift in industrial strategy and contextual scale.

Based on his words, here are the key “out of context” insights he is betting on that most of the industry currently treats as science fiction:

Subscribe now

Read more

The world’s most complex supply chain is currently being held hostage by a narrow strip of water. This article explores both the immediate risks and the potential silver linings emerging from the crisis.

As the sun rose over the Strait of Hormuz this morning, the usual parade of tankers and massive container ships remained conspicuously absent. Following the February 28 military strikes that upended the Middle Eastern balance of power, the Islamic Revolutionary Guard Corps’ blockade of this vital artery has done far more than just spike global oil prices above $100 per barrel. It has triggered a “geopolitical earthquake” that is rattling the very foundations of the $611 billion global semiconductor industry, threatening the production of everything from smartphones to advanced defense systems.

The Missing Ingredients

For the average consumer, a microchip is a finished product—a small piece of silicon that makes magic happen. For manufacturers, however, it is the world’s most “complex cake,” a product that takes over three months to bake through hundreds of microscopic stages. Today, that delicate recipe is missing several critical ingredients, and the pantry is looking increasingly bare.

“This industry runs on just-in-time logistics,” says one senior analyst at Rebound Electronics. “You cannot simply run down to the local store for a substitute when a ship carrying your specific high-purity chemicals is forced into a 14-day detour around the Cape of Good Hope. In the world of three-nanometer fabrication, a two-week delay is an eternity.”

The blockade has effectively severed the world’s access to Qatar’s liquefied natural gas (LNG) production, and with it, a massive portion of the global supply of helium. Simultaneously, South Korea—the world’s memory chip powerhouse—is reeling from a sudden, sharp shortage of bromine, an essential chemical used in etchings and flame retardants.

Fighting Back: Industry Mitigation Strategies

Faced with these existential threats, the titans of the semiconductor world are not sitting idle. While some sectors are scrambling, the biggest players have activated high-stakes mitigation plans to keep the lights on and the lasers firing.

• Stockpiling and Inventory Depth: Companies like SK Hynix have managed to project a sense of calm amid the chaos. The South Korean giant recently stated they have already secured a diverse supply chain and possess “sufficient helium inventory” to weather a prolonged disruption.

• Direct Supplier Intervention: Global Foundries took a more hands-on approach, activating their mitigation protocols the moment the blockade was announced. This involved establishing direct, real-time contact with key material suppliers to bypass traditional logistical chokepoints.

• Geographic Hedging: TSMC is accelerating its “Arizona strategy” with unprecedented speed. While they officially claim “no significant impact” currently, their actions tell a different story; they are pushing to install manufacturing tools in their second U.S. fab by late 2026, aiming for 3nm mass production by 2027 to ensure their most advanced tech isn’t trapped behind a blockade.

• Order Diversification: Rather than waiting for Israeli-based shipments from Tower Semiconductor to resume, its customers are shifting critical orders to Taiwanese mature-node chipmakers like UMC, VIS, and PSMC, effectively “voting with their volume” for safer manufacturing hubs.

  Share

The Power Paradox: Taiwan’s Energy Tightrope

In Taiwan, the crisis is hitting the power grid before it even reaches the factory floor. The Taiwan Semiconductor Manufacturing Company (TSMC), the world’s leading foundry, is a titan of consumption; it is on track to use 12.5% of the island’s entire electricity output by next year.

However, Taiwan’s energy security is precariously tied to the Middle East. The island relies on thermal power for 85% of its electricity, importing 70% of its crude oil and 30% of its LNG from the region. As oil prices skyrocket, the “Goldilocks economy”—characterized by low inflation and high growth—is under direct threat. The DBS report notes that every dollar added to a barrel of oil acts as a direct tax on the world’s computing power, raising production costs for every fab on the island.

The Parable of the Silver Lining

While the headlines scream of logistical chaos and rising costs, a quiet “silver lining” is beginning to emerge for those positioned to adapt. Industry insiders are pointing to the ancient parable of Sai Weng Shi Ma—the idea that what seems like terrible luck may ultimately prove to be a blessing.

1. The Sovereign AI Space Race

The conflict has provided a grim but highly effective demonstration of AI’s military utility. From real-time drone operations in Venezuela to battlefield analysis in Iran, AI has transitioned from a commercial luxury to “National Defense Infrastructure.” Consequently, governments worldwide are no longer content to rely on international data centers. There is a frantic, government-driven rush to build “Sovereign AI” infrastructure—computing power housed strictly within national borders. This is creating a new, “recession-proof” demand for high-end chips that ignores consumer electronics cycles.

2. The Israel-Taiwan Pivot

The conflict has also triggered a massive, global reshuffling of orders. Tower Semiconductor, Israel’s largest wafer foundry and a key supplier for Intel, Samsung, and Broadcom, is facing severe shipment disruptions. As these tech giants find themselves unable to get chips out of Israel, they are urgently rerouting their orders. The immediate beneficiaries are secondary Taiwanese foundries like VIS (Vanguard International Semiconductor) and PSMC, which are seeing a surge in business as they serve as a “safe harbor” for global manufacturing.

3. The Death of the Global Village?

China is doubling down on “domestic substitution,” forcing its local ecosystem to adapt and build redundancies overnight to insulate itself from Western-aligned chokepoints.

The New Normal: A Hardened Ecosystem

As the industry matures under fire, it is also turning toward more stable, independent energy foundations. The volatility of fossil fuels in the Middle East has reignited a desperate interest in nuclear power and massive energy storage systems (ESS) to keep the world’s data centers humming.

For years, conventional wisdom painted Taiwan as the world’s primary flashpoint of fragility due to regional tensions; yet, this crisis has flipped the script. It is the Middle Eastern conflict that has proven the absolute necessity of Taiwan’s value as a resilient alternative, as it is where customers turn to when shipments from Israel are stuck.

By demonstrating unparalleled agility and providing a diversified regional supply chain when other hubs faltered, Taiwan has transitioned from a point of concern to the industry’s most critical safe harbor. However, we should not forget that Taiwan also has its vulnerabilities besides geopolitical risks.

Ultimately, this crisis serves as a stark reminder that disruption often strikes from the least expected directions—much like the global lockdowns of years past. The enduring question for the tech world is no longer how to optimize, but how to remain prepared for the unpredictable shocks of tomorrow.

Subscribe now

Reference:

BRIEF-TSMC, In Response To Question On Possible Raw Material Supply Chain Disruption From Iran War: We Do Not Anticipate Any Significant Impact At This Time

Chip Industry on Alert as Middle East Conflict Risks Disrupting Supply Chains

Impact of US-Iran War on Stock Market

Iran crisis could disrupt supply of key chipmaking materials, South Korea warns

Qatar Helium Halt Threatens Global Chip Supply Amid Iran Conflict

UMC honorary vice chairman warns US-Iran war unlikely to end quickly, urges tech sector to build Taiwan value

What this patent actually does

The patent describes a system where the platform takes a pretrained large language model and fine-tunes it on one specific user’s historical data: posts, comments, likes, messages, reactions, and more.

The system then ranks incoming content in the feed to decide which items this user would most likely care about, similar to how feed ranking systems work today.

For each selected item, the system builds a context-rich prompt (post content, prior interactions, relationship signals) and asks the user-specific model: “What would this person do here?”—like, comment, react, or reply.

Finally, it posts that interaction on the platform on behalf of the user, potentially even using different model versions to simulate the user at different ages.

In short: Collect user history → Fine‑tune user model → Rank content → Build contextual prompt → Predict interaction → Post as the user.

Share

Technical lens: key design ideas

1. User‑specific language models, not just one big generic model

Instead of a single general‑purpose LLM with clever prompting, the patent focuses on re‑training a base model on data from a single target user. The goal is not just to produce a plausible reply, but to approximate how this particular person tends to speak, react, and prioritize their social interactions on the platform.

2. Ranking as “who I would bother to respond to”

The system doesn’t respond to everything; it first runs a ranking step to predict which posts the user would realistically engage with. This means the AI twin is modeling not only language, but also social selectivity—who gets a reply, who gets ignored, and what kind of content actually triggers a reaction.

3. Context‑aware prompts, not zero‑shot replies

When generating a response, the model doesn’t just see the raw post; it can also be conditioned on contextual signals like prior conversations, relationship strength, and user attributes of the person who posted. In practice, this turns the “AI twin” into an agent acting in an evolving social environment, not just a text generator reacting to isolated inputs.

Product and business angle: why would Meta care?

From a product KPI perspective, this extends the “lifetime” of engagement beyond a user’s active usage—potentially beyond their biological lifetime. Even when a user is inactive or deceased, their profile could still generate interactions and content, helping maintain the density and continuity of social graphs. More broadly, this looks like an early commercial template for personal AI agents: systems that can handle routine social decisions and interactions on your behalf using first‑party behavioral data at platform scale.

Ethical and societal questions: beyond pure tech

“Is this really them?” – ownership of digital persona Technically, the AI agent is a statistical approximation trained on past data, yet it speaks and acts under the user’s name and identity. When the agent expresses views that family members or the user (while alive) would disagree with, who holds responsibility—the platform, the model designers, or the historical data subject?

Consent and revocation by design

The patent focuses on system architecture, not real‑world consent flows, but actual products would need to answer hard questions. Did the user explicitly opt in to a post‑mortem AI, who controls it after death, and how easy is it to shut it down if the family or the user (while still alive) changes their mind?

Psychological impact: comfort or captivity?

For some, ongoing interactions with an AI version of a deceased person might offer comfort or help with grief. For others, it could prolong mourning, blur reality, or create emotionally manipulative feedback loops—especially when combined with engagement‑driven ranking systems.

We are designing technologies to extend relationships

Early social products were designed to “connect people.” Systems like the one in this patent are about extending a relationship with a digital persona, even when the original human is absent.

As AI systems become capable of acting as our social proxies, we’re not just delegating tasks—we’re delegating fragments of identity and decision‑making to models owned and operated by platforms.

For teams building AI products today (including us at Deeli AI), the critical question is shifting from “Can we do this?” to “How much of ourselves are we willing to outsource—and under whose terms?”

If LinkedIn offered you a toggle today that said, “Let an AI trained on your activity keep speaking for you after you are gone,” would you click yes? Or no?

Subscribe now

About the author: Alan Chen is the Head of Growth of Deeli.ai.

Previous IP Insight articles:

Recent headlines around silicon photonics often highlight one observation: TSMC has caught up with and now surpassed Intel in patent filings, even opening a visible lead.

That comparison is not without value. But if the discussion stops at who has filed more patents, it misses the more interesting question: what are those patents actually meant to accomplish?

Even though both companies are investing in silicon photonics, the objectives behind those portfolios appear to be different. TSMC is integrating photonics into its advanced packaging platform to deepen long term customer dependence. Intel, by contrast, appears to be assembling a comprehensive system-level design toolkit that it can deploy internally and potentially leverage in partnerships or licensing.

If you missed the previous article, read here:

Same Technology, Different Priorities

A review of several analyses covering CPO, co-packaged optics, and optical interconnect patents quickly reveals a distinction. Many of Intel’s patents focus on system-level architecture. They address questions such as:

• Where should the photonic engine be placed?

• How should package layers be stacked?

• How should cooling and routing be designed?

The filings often resemble complete system blueprints.

TSMC’s patent focus, on the other hand, tends to concentrate on manufacturability and integration.

The emphasis is on how to reliably fabricate photonic components at wafer scale, how to integrate them with logic dies and HBM within advanced packaging, and how to manage thermal performance and long term reliability.

In simple terms, Intel’s portfolio often reflects architectural design thinking. TSMC’s portfolio reflects process, materials, and integration execution. Both are silicon photonics patents. Their strategic functions differ.

Subscribe now

TSMC: Making Silicon Photonics a District Inside 3DFabric

For TSMC, silicon photonics does not appear to be positioned as a standalone business unit. Instead, it is being folded into its broader 3DFabric umbrella, which already includes CoWoS, SoIC, and InFO advanced packaging technologies.

Silicon photonics effectively becomes another functional zone within that ecosystem, allowing compute, memory, and high-speed interconnect to be delivered together as an integrated solution for AI customers.

COUPE as a Platform Component

COUPE, frequently referenced in recent discussions, can be understood less as a standalone product and more as an optical link module integrated into a broader packaging solution.

It combines photonic elements and driver circuitry in a form factor designed to co-package with GPU and HBM, becoming part of a high-end AI packaging stack.

TSMC’s positioning suggests that COUPE is intended as a reusable engine rather than a one-off demonstration. Different customers and product lines could build upon the same foundational module rather than starting from scratch each time.

In this sense, silicon photonics functions as an additional capability within 3DFabric, not as a separate vertical business.

Locking Process Knowledge In the Fab

TSMC’s silicon photonics patents frequently revolve around several recurring themes:

• Wafer-level photonic integration on 300mm CMOS processes, including optical structures that improve fiber alignment and production efficiency.

• Interconnect design between photonic dies, logic dies, and HBM stacks, including TSV, bump, and redistribution layer optimization.

• Thermal dissipation, mechanical stress management, and reliability improvements within complex stacked packages.

These are fundamentally manufacturing and integration problems. Once captured in patents, however, they create a protective layer around TSMC’s production methods.

If a customer later seeks to replicate a similar GPU plus HBM plus photonics configuration at another foundry, the challenge is not only technical re-engineering but also careful navigation around TSMC’s intellectual property.

Commercial Objective: Long-Term Stickiness

Strategically, the objective is platform stickiness. If a customer outsources a single 5nm or 3nm generation to TSMC, switching suppliers in a future node is difficult but not impossible.

If, however, the entire AI platform, compute, memory, and optical interconnect, is deeply integrated within TSMC’s 3DFabric ecosystem, migration becomes substantially more complex.

In that context, the value of TSMC’s silicon photonics patents lies less in royalty potential and more in reinforcing long term customer dependence across multiple product generations.

Share

Intel: Building a System-Level Arsenal

Intel’s starting point differs. As a company that designs CPUs, GPUs, accelerators, switching silicon, and networking products, silicon photonics initially serves as a way to embed optical I/O capabilities directly into its own product portfolio.

At the same time, its patent distribution suggests preparation for broader ecosystem engagement.

Architectural and Layout Level Thinking

Many of Intel’s CPO and silicon photonics patents focus on overall architecture rather than incremental process refinements.

Examples include:

• Designs placing photonic engines on both sides of a substrate to increase optical channel density without expanding the footprint

• Architectures that position modulators and detectors close to compute cores to minimize electrical to optical conversion distance

• Integration approaches using technologies such as EMIB to bring compute chiplets and photonic chiplets into closer proximity

These patents often read like complete layout strategies. Optical placement, thermal paths, and routing are considered holistically.

Internal Use With External Optionality

This intellectual property directly benefits Intel’s own product lines. Future XPU, switching, and networking designs can draw upon a prepared design framework rather than building from scratch.

At the same time, the geographic distribution of filings across the United States, Europe, and China suggests preparation for collaboration, licensing, or standards negotiations.

This mirrors Intel’s approach in other packaging technologies, such as glass substrate initiatives, where internal deployment coexists with potential external engagement.

An Arsenal Rather Than a Factory

A useful analogy highlights the contrast.

• TSMC is embedding silicon photonics into its manufacturing infrastructure.

• Intel is embedding silicon photonics into its architectural design playbook.

The former says: If you want this integrated packaging plus optical connectivity solution, we have the production flow and capacity.

The latter says: if you are interested in this system architecture, we have a portfolio of designs and intellectual property that can form the basis of collaboration.

In that sense, Intel’s approach resembles building an arsenal or workshop. Not every tool will be deployed immediately, but if market direction shifts, the necessary designs and patents are already in place.

From a Customer Perspective: Two Different Propositions

From the viewpoint of large AI customers, the distinction translates into different partnership models.

Choosing TSMC: Manufacturing and Integration Platform

For companies such as NVIDIA and major cloud providers, TSMC represents a relatively neutral manufacturing and integration partner.

Advantages include:

• Consolidating leading-edge process, HBM packaging, and optical integration within a single supplier

• Reducing coordination complexity and execution risk across multiple vendors

The tradeoff is platform dependence. Deep architectural coupling with 3DFabric and silicon photonics integration increases switching costs significantly.

Share

Choosing Intel: System Architecture and IP Engagement

Working with Intel introduces a more complex dynamic.

Intel possesses a comprehensive XPU plus photonics plus packaging design framework, which may accelerate system-level innovation for certain partners.

At the same time, Intel competes in CPUs, accelerators, switching, and networking. The relationship may involve both collaboration and competition, requiring careful consideration of roadmap alignment and control.

For customers, partnering with TSMC resembles selecting a long-term manufacturing and integration platform. Partnering with Intel resembles engaging with a system architecture and IP collaborator that may also operate in adjacent competitive spaces.

Conclusion: Looking Beyond Patent Counts

The observation that TSMC has surpassed Intel in silicon photonics patent filings is factually valid. But concluding from that alone that one company is leading and the other is falling behind oversimplifies the picture.

In a domain that spans manufacturing, packaging, and system architecture, more nuanced questions are required:

• Are the patents primarily securing manufacturing and integration processes, or system-level architectural control?

• Are they reinforcing platform stickiness, or building leverage for licensing and standards negotiations?

• Are they tied to defined production roadmaps or positioned as strategic options awaiting broader market inflection?

Under the label of silicon photonics, TSMC appears to be expanding a commercial ecosystem designed for customer integration. Intel appears to be organizing a versatile design and intellectual property toolkit for both internal and external strategic use.

The next time a headline highlights patent totals, it may be worth asking a more fundamental question—what strategic game is each company playing?

Subscribe now

About the author: Alan Chen is the Head of Growth of Deeli.ai.

Editor’s Note: The IP Insights Series is a collaborative initiative between Deeli AI, Mission International Patent & Trademark Office, and TechSoda, powered by the Deeli AI platform to analyze patents and papers.

When silicon photonics was discussed over the past decade, the company most often associated with it was Intel. That association is beginning to shift.

Recent patent data in the United States suggests a divergence in activity. TSMC has increased its filings in core silicon photonics technologies over the past two years, while Intel’s annual filings in this area have declined.

Patent counts do not equate to technical superiority. However, they do provide insight into where companies are allocating capital, engineering resources, and long-term strategic focus. In that sense, the divergence is meaningful.

The contrast reflects two very different business realities. On one side is a foundry responding to accelerating AI customer roadmaps. On the other is a large IDM navigating capital intensity, process node catch-up, product competition, and structural transformation.

Silicon Photonics as an AI Era Bottleneck Solution

Silicon photonics integrates optical components directly into silicon chips or advanced packaging, enabling data transmission via light instead of electrical copper interconnects.

In the AI era, this capability is becoming increasingly important.

As GPU, TPU, and accelerator performance continue to scale, bottlenecks are shifting away from raw compute. Instead, interconnect bandwidth and power efficiency between chips and between racks inside data centers are emerging as critical constraints.

This is where CPO (co-packaged optics) and optical I O architectures enter the discussion. By embedding optical engines closer to compute silicon, electrical path lengths are reduced, signal conversion losses are minimized, and higher bandwidth can be achieved at lower power consumption.

Intel has been an early and credible participant in silicon photonics, integrating optical technologies into server and networking applications and demonstrating multiple proof-of-concept systems.

However, since 2023, patent activity suggests a shift in intensity.

The Patent Divergence

Industry analyses of US-based silicon photonics patents indicate that TSMC and Intel were closely matched as recently as 2023.

In 2023,

• TSMC filed approximately 46 relevant patents

• Intel filed approximately 43

In 2024

• TSMC increased to roughly 50

• Intel declined to about 26

The magnitude of this change suggests a shift in allocation rather than a statistical fluctuation.

This trend is consistent with a broader recalibration at Intel. Between 2015 and 2020, Intel expanded patent filings aggressively across multiple technology domains. Since 2023, overall filings have moderated, particularly in certain frontier areas.

Silicon photonics appears to be part of that broader shift toward selectivity. In other words, the divergence is less about photonics itself and more about capital allocation under different business models.

Share

Why TSMC Is Increasing Activity

AI Customer Roadmaps Are Driving Integration Requirements

Large language models (LLMs) and AI training clusters are pushing data center architectures to new scales. Compute can scale by adding more GPUs. Memory capacity can scale through HBM stacking. But interconnects between GPUs and between racks become increasingly constrained by power and bandwidth when relying solely on copper-based architectures.

CPO and silicon photonics provide a potential pathway to address these constraints.

For TSMC, this is not a speculative research topic. Major customers such as NVIDIA and AMD are designing future architectures that depend heavily on advanced packaging integration.

Optical I O is increasingly discussed within those roadmaps.

From a foundry perspective, enabling that integration strengthens platform relevance.

From Demonstration to Production Alignment

Reports indicate that TSMC intends to integrate silicon photonics solutions into advanced packaging platforms such as CoWoS and SoIC, targeting 1.6T optical module generations around 2025 and broader scaling thereafter.

This alignment with production timelines is important. It signals integration into customer roadmaps rather than isolated demonstration efforts.

Architectures such as COUPE, Compact Universal Photonic Engine, illustrate this approach. Public descriptions suggest a three-layer stack combining a 6nm electronic die, a 65nm photonic die, and an intermediate integration layer designed to support both horizontal and vertical optical connectivity.

The emphasis appears to be on modular reuse across multiple customer programs rather than one-off custom designs.

In this context, patent filings function as protective infrastructure around a production-oriented platform strategy.

Platform Differentiation in the Foundry Model

Unlike an IDM that sells end products, a pure play foundry competes on process technology and integration capability.

TSMC’s patent focus in silicon photonics appears concentrated in areas such as:

Integration within 300mm CMOS manufacturing, advanced packaging integration of GPU, HBM, and optical engines, thermal management, TSV structures, passive alignment, and material reliability.

If these integration methods are protected, customers designing large-scale AI packages may face higher switching costs.

From a strategy perspective, silicon photonics strengthens platform stickiness for a foundry that directly supports long-term wafer and advanced packaging revenue.

Why Intel’s Activity Appears More Selective

Intel remains a significant technology holder in silicon photonics. The moderation in filings should not be interpreted as abandonment.

However, Intel is simultaneously investing in advanced nodes such as 18A, expanding fabrication capacity in the United States and Europe, defending CPU and accelerator competitiveness, and building out its foundry services business.

Capital expenditure requirements are substantial. R&D prioritization becomes unavoidable. In that environment, patent strategy tends to become more focused on areas with clearer near-to-mid-term revenue linkage. Intel has also adjusted certain optical communications activities. For example, transceiver-related assets were transferred to Jabil, reflecting the refinement of product focus.

In advanced packaging discussions, licensing and ecosystem approaches are increasingly emphasized alongside internal deployment. Rather than broad expansion, the pattern suggests protection of core IP while narrowing the scope of new filings. From a strategic standpoint, silicon photonics may currently occupy a medium to long-term option position within Intel’s broader portfolio, rather than a near-term growth driver.

Two Strategic Realities on the Same Track

The contrast is not simply about who believes in silicon photonics more. For TSMC, silicon photonics can extend an already dominant advanced packaging platform. AI customers are actively scaling orders for leading-edge process nodes and 3D integration. Optical integration represents a logical extension of that trajectory.

For Intel, the strategic landscape is more complex. Process leadership recovery, product competitiveness, fab construction, and foundry expansion all compete for capital and management focus.

Under those conditions, even important technologies may advance at a measured pace.

What Patent Counts Do and Do Not Tell Us

Patent volumes function as indicators of strategic emphasis, not definitive measures of technical leadership or commercial outcome. In silicon photonics, the more relevant questions are structural: Are these filings reinforcing a manufacturing and packaging platform that customers will build around for the next decade? Or are they consolidating a defensible intellectual property position that preserves long-term strategic leverage?

TSMC’s recent activity suggests an effort to deepen platform stickiness, extending its advanced packaging ecosystem into optical integration and embedding itself more tightly into AI customer roadmaps.

Intel’s recent pattern suggests a different emphasis: protecting core architectural and integration IPs while managing capital discipline across multiple strategic priorities.

One strategy compounds platform dependency. The other builds an intellectual property arsenal.

Same technology. Two strategic games.

How those two approaches ultimately reshape bargaining power within the AI supply chain remains an open question — and one that will define the next phase of competition in silicon photonics.

In the next article (IP Insight #4), we take a further deep dive into the portfolios and what they tell us about the two semiconductor giants’ strategies.

Subscribe now

About the author:

Editor’s Note: The IP Insights Series is a collaborative initiative between Deeli AI, Mission International Patent & Trademark Office, and TechSoda, powered by the Deeli AI platform to analyze patents and papers.

Previous IP Insight articles:

Nebius just paid $275 million for a company most people never heard of. But if you've been following the pattern from 2025's biggest AI deals, this move follows a clear pattern.

In early February 2026, Amsterdam-based AI cloud service provider Nebius announced it would acquire Tavily, an Israeli startup specializing in "agentic search." The deal is valued at $275 million in initial cash consideration, with potential additional payments bringing the total to as much as $400 million contingent on performance milestones. While it might seem like just another tech acquisition, place it alongside 2025's landmark AI deals, and a clear pattern emerges about where the real value is concentrating in the AI stack.

What the 2025 Mega-Deals Taught Us

A comprehensive report by Deeli AI analyzing 2025's AI M&A landscape, "Beyond the Headlines: Nvidia-Groq, Meta-Manus, and How to Read the Next Wave of AI Deals," identified over $150 billion in disclosed deal value across the AI stack. The report found that capital wasn't spreading evenly but concentrating on a few critical layers:

Nvidia's $20B acquisition of Groq wasn't about buying a competitor. It was about securing a "real-time inference lane" optimized for the specific needs of AI agents: ultra-low latency, deterministic token generation, and predictable performance for multi-step workflows. Groq's LPU architecture trades flexibility for speed and reliability, targeting exactly the workloads where traditional GPUs over-provision or miss responsiveness targets.

Meta's $2B+ purchase of Manus validated that general-purpose agents can be real businesses, not just demos. Manus had scaled to hundreds of millions in revenue by becoming something closer to a "virtual colleague" than a chatbot: users delegated complete workflows (research, drafting, follow-ups, scheduling), and Manus handled them end-to-end with minimal hand-holding. The key was workflow ownership, not just clever prompts.

The Deeli AI report's central finding: the most valuable AI assets are shifting from model weights and flashy interfaces to the infrastructure that makes agents reliable, governable, and economically viable in production. Control points now sit at the intersection of interfaces (how agents interact with capabilities), economics (how costs are surfaced and managed), and reliability (how behavior is monitored and guaranteed).

Where Nebius-Tavily Fits the Pattern

Seen through this lens, Nebius buying Tavily is the logical next chapter. Here's what Nebius actually bought:

Tavily provides search and retrieval infrastructure purpose-built for AI agents. When an agent needs to research a market, qualify leads, or pull fresh data to complete a task, Tavily handles the querying, parsing, and structuring so the agent gets clean, model-ready context instead of raw HTML. Its customers include Fortune 500 companies and major AI platforms, with over 3 million SDK downloads per month. Tavily had become a plumbing that serious agent builders quietly depend on.

Just as Groq created a "fast inference lane" for generating tokens, Tavily creates a "retrieval lane" for acquiring the right context with predictable latency and cost. Both are reusable building blocks that sit deep in the stack, not end products themselves.

By integrating agentic search natively, Nebius now controls how agents on its platform discover and use search, how it's priced alongside compute (per query, per task, per workflow), and safety, compliance, and governance across all agent workloads. This is a classic "control plane" strategy: you acquire the layer where traffic, spending, and policy converge.

The Emerging Pattern: From Models to Infrastructure

Looking at these deals together reveals a fundamental shift in how the AI stack is being valued and consolidated:

Infrastructure is re-architecting around agents. We're moving from "GPU clouds" and "model APIs" to agent-first platforms that compete on how well they support the full agent lifecycle: low-latency multi-step workflows, native primitives (search, tools, memory, evaluation), and pricing that maps to tasks rather than tokens. Nebius-Tavily is a concrete step in that direction. By owning both compute and search, Nebius can price holistically around complete workflows like "research a market" or "qualify 100 leads."

M&A is clustering around workflow chokepoints. The biggest 2025 deals targeted specific bottlenecks in agent workflows where capacity, data, or control planes are scarce and hard to replace: specialized inference silicon (Groq), vertically integrated infrastructure (CoreWeave acquiring Core Scientific, AMD buying ZT Systems), observability and evaluation (Palo Alto Networks acquiring Chronosphere), and agents that own complete workflows (Manus). Tavily adds retrieval and context assembly to that list. Expect more deals targeting orchestration engines, safety frameworks, vertical data hubs, and credentialing systems.

The competitive advantage is shifting to control and pricing. The next wave of AI moats won't be "better models" but control over how capabilities are exposed, priced, and governed. Nebius now controls how search works for every agent on its platform. That's leverage over developer experience, unit economics, and compliance. The companies winning in this environment will own the infrastructure agents rely on to see, remember, act, and be trusted in production.

Implications for the Tech Industry's Future

The consolidation we're witnessing signals a fundamental restructuring of how AI capabilities will be built, distributed, and monetized. As platforms vertically integrate key pieces of the agent stack (from compute and search to orchestration and safety), the industry is moving toward a model where a handful of large platforms control the complete infrastructure that makes autonomous AI work in practice. For startups, this creates a narrowing window to build strategic value: the tools of the agent economy (search, workflow control, testing, safety) are becoming acquisition targets while industry standards for agent-to-infrastructure interfaces are still being established, and independent players can still establish market positions. For developers and enterprises, choosing which ecosystem to build on is becoming a more consequential decision, as integration depth and switching costs increase while fragmentation across incompatible platforms becomes the norm. And for end users, the trade-off is becoming clearer: more reliable, capable AI experiences that "just work," in exchange for fewer choices about which platforms power those experiences and less visibility into how those platforms govern agent behavior, costs, and access.

This analysis draws on insights from Deeli AI's industry report published in January 2026.

Subscribe now

About the author: Alan Chen is the Head of Growth of Deeli.ai

Editor’s Note: The IP Insights Series is a collaborative initiative between Deeli AI, Mission International Patent & Trademark Office, and TechSoda, powered by the Deeli AI platform to analyze patents and papers.

Previous IP Insight article:

The recent US$252 million settlement between the U.S. Department of Commerce and Applied Materials (AMAT) and Applied Materials Korea (AMK) provides more than just a legal headline—it offers a critical missing piece of the puzzle regarding China’s semiconductor progress. When viewed alongside record-breaking trade data from Taiwan, a clear picture emerges of how China eventually managed to achieve a 70% yield on 7nm chips claimed by an analyst despite aggressive Western sanctions.

In the first eleven months of 2025, Taiwan’s exports of high-end glass fiber fabric surged to a record US$350 million—a 39.9% year-on-year increase, while nearly 60% was shipped to China. While these shipments are perfectly legal, they serve as a high-fidelity “thermometer” for China’s AI ambitions. As high-performance glass fiber fabric is the essential structural backbone for AI servers and IC substrates, this surge confirms that China is not just making chips, but successfully integrating them into large-scale AI infrastructure.

AI chips generate extreme heat and require high-frequency signals, which in turn require "ultra-thin, high-quality" glass fiber. This explains why the 39.9% increase in export value isn't just about volume—it's about price and complexity.

The Role of the “Smuggled” Ion Implanters

The AMAT settlement centers on the unauthorized shipment of ion implanters—highly specialized machines used to “dope” silicon wafers to create transistors. Between 2021 and 2022, dozens of these machines were rerouted through South Korea to bypass “Entity List” restrictions on SMIC, China’s leading foundry.

The arrival of these precision tools likely provided the technical foundation for SMIC’s yield breakthrough. While China remains barred from the latest EUV (Extreme Ultraviolet) lithography, the availability of high-end ion implanters, combined with Self-Aligned Quadruple Patterning (SAQP) on older DUV machines, has allowed SMIC to bridge the gap.

According to BIS, in 2021 and 2022, AMAT violated BIS’s requirement to obtain a license before shipping to a company on the Entity List by shipping ion implanters first to AMK in Korea for assembly, and then onward to China, without applying for and receiving an export license. The value of merchandise illegally shipped was approximately $126 million.

Judging from the fact that the ion-implanters sold by AMAT and AMK to China are used in advanced node semiconductor manufacturing processes while the glass fiber fabric form the structural backbone of PCBs and IC substrates used in AI servers, chips, and mobile devices, the surge in China’s share in Taiwan’s glass fiber fabric exports over the past six years may not be a coincidence.

The data recently released by Taiwan’s Ministry of Finance (MOF) showed that China’s share of Taiwan’s glass fiber fabric increased from 40% to 57.3% between 2020 and 2025. (See chart)

Share

As AI and high-speed computing advance, ultra-thin, high-quality electronic-grade glass fiber fabric has become an essential foundation for next-generation electronics.

While SMIC is reportedly experimenting with 5nm processes, yields remain poor. However, at 7nm, China has found a “sweet spot” that allows for mass production of processor chips like Huawei’s Ascend 910 series.

The System-Level Countermove

Because China cannot yet match the raw transistor density of NVIDIA’s latest Blackwell chips, they have pivoted to what Nobunaga Chai, a senior semiconductor analyst and deputy director at Cloud Express, calls a “disruptive redesign” at the system layers. By using advanced packaging—supported by that record-setting Taiwanese glass fiber fabric —and optical interconnects, Huawei is compensating for individual chip limitations through superior server architecture.

The question is, since EUV is banned, can China really manufacture enough advanced chips to be used in their AI servers? China claims that it is driving towards self-sufficiency in AI computing and waged a “de-Americanization” campaign to kick US products out. Both SMIC and Shanghai Huali Microelectronics Corporation (HLMC) are capable of manufacturing 7nm chips with Deep Ultraviolet lithography equipment.

SMIC posted record revenue and strong earnings growth in 2025, even as gross margins declined, likely reflecting a production ramp at 7nm-class nodes.
Fourth-quarter and full-year sales reached new highs, driven by China’s push for semiconductor self-sufficiency. However, gross margin fell to 19.2% in 4Q25 and is expected to remain under pressure, as higher costs of multiple patterning with DUV lithography machines at 7nm-equivalent processes weighed on profitability. The results suggest SMIC is prioritizing advanced-node output growth over near-term margins.

SemiAnalysis wrote in 2023 that to prevent China from achieving high-volume 7nm production would require restricting not only advanced DUV tools like ArF immersion (ArFi), but also other DUV technologies capable of reaching a 40nm minimum metal pitch. Even without ArFi, techniques such as self-aligned quadruple patterning (SAQP) using dry ArF lithography can still achieve 7nm-class features, albeit at higher cost and lower efficiency. As a result, export controls would need to extend beyond ArFi to be fully effective, especially given national security considerations.

China has continued purchasing multiple types of DUV lithography tools from ASML in large volumes, accounting for 36% of ASML’s net system sales in Q4 2025 and 33% for the full year. The AMAT–AMK case demonstrates that U.S. export controls—relying on a whack-a-mole approach of Entity Lists and targeted restrictions—have failed to meaningfully curb China’s access to critical semiconductor manufacturing equipment.

Subscribe now

TechSoda connects the dots for you. Please consider becoming a subscriber so as not to miss any important information.

Read more

Vietnam is no longer content with being the world’s back-end assembly line. Long a hub for the testing and packaging of chips designed elsewhere, the Southeast Asian nation is now aggressively moving up the value chain. Two major announcements from national champions FPT and Viettel recently signal a decisive shift toward “sovereign technology”—a bid to design, manufacture, and control its own semiconductor destiny.

A Global Hub: The Current Investment Landscape

Vietnam has already successfully attracted multi-billion-dollar investments from the world’s most significant semiconductor players. While the country’s primary strength has historically been in packaging & testing (OSAT), there is a rapidly growing footprint in IC Design and R&D.

The Strategic Blueprint: Vision 2050

Underpinning these investments is a formal national strategy (Decision 1018/QD-TTg) that outlines a path toward complete technological autonomy. The government’s vision is summarized by the formula C = SET + 1:

• C (Chip): The ultimate goal of semiconductor mastery.

• S (Specialized): Focusing on specialized chips like AI and IoT.

• E (Electronics): Strengthening the domestic electronics industry.

• T (Talent): Leveraging Vietnam’s human resource potential.

• +1 (Vietnam): Positioning Vietnam as the “plus one” safe destination for global supply chains.

The Three-Phase Roadmap

The strategy breaks down Vietnam’s ambitions into three distinct chronological horizons:

1. Phase 1 (2024–2030): Foundation Building. Vietnam aims to become a global semiconductor talent hub, training 50,000 engineers. Targets include establishing 100 design firms, one small-scale fab, and 10 OSAT plants, with industry revenue exceeding $25 billion.

2. Phase 2 (2030–2040): Regional Hub. The focus shifts to combining FDI with domestic self-reliance. Goals include 200 design firms and two chip fabs, with industry revenue climbing to $50 billion.

3. Phase 3 (2040–2050): Global Leadership. Vietnam aspires to be a world leader in semiconductors and electronics, mastering R&D with at least 300 design firms and three fabrication plants. Revenue is targeted to surpass $100 billion.

   Share

The Manufacturing Milestone: Viettel’s Fabrication Ambition

For years, the “holy grail” of semiconductor independence has been the “fab”—the fabrication plant where silicon wafers are actually printed. Historically, Vietnam has lacked this capability, relying on external foundries.

In January 2026, state-owned telecom giant Viettel changed this narrative by beginning construction on Vietnam’s first-ever semiconductor fab in Hanoi’s Hoa Lac Hi-Tech Park. This facility represents a “first leap” into true chip fabrication, aiming to cover the full lifecycle from design to manufacturing. By leading this project, Viettel is fulfilling the Phase 1 mandate to secure critical infrastructure.

Bridging the Gap: FPT’s Advanced Semiconductor Facility

While Viettel focuses on the hardware of fabrication, FPT—Vietnam’s leading technology firm—is tackling the ecosystem from a different angle. In early 2026, FPT announced the establishment of its own semiconductor testing and packaging plant in Bac Ninh. Notably, this is the first such facility to be wholly owned and operated by a Vietnamese entity.

FPT’s strategy is twofold:

1. Capacity Building: The new facility accelerates the R&D process for FPT’s power management and IoT chips.

2. Human Capital: FPT serves as a primary training ground to meet the 50,000-engineer target by 2030.

The “Sovereign” Strategy: Why Now?

Vietnam’s push to build a sovereign supply chain is shaped by a dual imperative: the global “China+1” strategy and the need to avoid the middle-income trap. As many information and communications technology (ICT) manufacturers—including Chinese firms—have shifted production to Vietnam to de-risk from U.S. tariffs and geopolitical uncertainty, ensuring reliable access to semiconductors has become a strategic priority. Given that chips are critical inputs for these end products, strengthening the semiconductor supply is a natural and necessary step in Vietnam’s industrial upgrade.

By controlling design, fabrication, and packaging, Vietnam aims to retain higher profit margins. The National Innovation Center (NIC) plays a central role in this, serving as the “bridge” between global EDA providers like Synopsys and local startups.

Vietnam’s semiconductor market is valued at about US$10.16 billion in 2025 and is projected to grow to US$16.51 billion by 2030, reflecting a 10.23% compound annual growth rate, according to Mordor Intelligence. This growth positions Vietnam as a key alternative manufacturing hub as global companies diversify away from China-centric supply chains.

Foreign direct investment from major players such as Intel, Samsung, and Amkor has anchored Vietnam’s capabilities in advanced assembly and testing, while expanding demand from smartphones, IoT, and AI applications supports sustained volume growth over the long term.

The Vietnamese government’s National Semiconductor Strategy (2024–2030), combined with preferential trade relations with the United States, is accelerating localization efforts in semiconductor packaging and design.

Despite remaining challenges—such as dependence on imported ultra-high-purity gases—Vietnam’s rare-earth mineral reserves provide a strategic advantage that few competing markets can match, strengthening its long-term position in the global semiconductor ecosystem.

Challenges on the Horizon

Despite the momentum, the path is fraught with challenges. Fabrication requires billions in constant reinvestment. Furthermore, the “C = SET + 1” formula relies heavily on “T” (Talent). While the numbers are growing, the transition from basic software testing to complex high-end hardware design remains a significant hurdle for the local workforce.

Conclusion

The dual-pronged attack by FPT and Viettel, codified by the 2050 National Strategy, marks the end of Vietnam’s era as a passive participant. By investing in both the intellectual property of design and the physical infrastructure of fabrication, Hanoi is sending a clear message: the future of Vietnamese technology will be “Made in Vietnam,” from the silicon up.

Subscribe now

References

• FPT Press Release: Establishment of Advanced Semiconductor Manufacturing Facility (Yahoo Finance)

• Business Times: Vietnam Takes First Leap in Chip Fabrication via Viettel-led Fab

• The Diplomat: Vietnam’s Semiconductor Strategy Explained (Decision 1018/QD-TTg Analysis)

• Vietnam Semiconductor Market Size & Share Analysis - Growth Trends and Forecast (2025 - 2030)

• Vietnam’s Semiconductor Pivot: From ATP Workhorse to Front-End Contender
  
  

Executive Summary: The “System-Level Foundry” Shift

Understanding TSMC’s current Intellectual Property (IP) layout is critical because it reveals a fundamental transformation: TSMC is no longer just shrinking transistors; it is architecting an integrated AI infrastructure. By cross-referencing recent patent filings with the January 15th earnings call, three strategic imperatives emerge:

1. Breaking the Memory/Power Wall: The pivot toward BEOL (Back-End-Of-Line) interconnect innovation, BEOL compatible logic devices, and 3D IC structures (roughly 25–30% of the patents in our sample) indicates that TSMC increasingly views “interconnect and thermal management,” rather than front-end node scaling alone, as the key bottleneck to be addressed over the coming decade.

2. Packaging as a Primary Moat: By elevating CoWoS and SoIC as a second strategic battleground alongside advanced wafer fabrication, TSMC is leveraging technical complexity and tight integration to lock in high-value AI customers such as NVIDIA and AMD, and to raise the competitive bar for alternative foundries and OSATs.

3. Financial Fortification: A growing portfolio of patents around equipment design and process control effectively reinforces TSMC’s cost and yield position, supporting its ambition to sustain around 60% plus gross margins even as overseas fabs and the N2 ramp introduce 2–4 percentage points of structural margin dilution.

1. AI/HPC Growth Driving Surge in Advanced Node + 3D Structure Patents

• Earnings Call Summary: Management explicitly stated that the revenue CAGR for AI accelerators will approach 55% from 2025–2029. The HPC platform already accounts for over half of total revenue and will continue to grow.

• Patent Trends: In the past two years, a massive number of patents have been filed in fin structure stress engineering (designing and tuning stress in FinFET channels and layouts), hybrid fins, BEOL compatible logic, and TSV plus guard rings. These are designed to maintain high performance, high signal integrity, low power, and 3D‑stackable logic foundations beyond the N3/N2 nodes.

Insight: TSMC views AI growth as “structural and long-term.”

Instead of simple line-width shrinking, resources are being poured into architectures like GAAFET, BEOL logic, and 3D-IC that can sustain growth for a decade. This grants TSMC significant leverage in architectural flexibility and 3D integration for future generations (N2P, A16).

2. AI Capacity Tightness → Significant Increase in Packaging/Thermal Patents

●Earnings Call Summary: Management repeatedly emphasized that AI-related capacity is “extremely tight.” Capital expenditure (Capex) has been raised significantly, with a large portion dedicated to expanding advanced packaging and AI-specific packaging capacity.

● Patent Reflections:

o Stress Management: Stress-release lines and reinforcement structures within silicon or organic interposers/substrates to solve mechanical reliability issues in multi-chip packaging.

o Mechanical Strength: In Fan-out/SoIC packaging, specific die arrangements and molding/cutting designs are used to improve mechanical integrity.

o Active Cooling: Integration of thermal modules with cavities and embedded TECs (Thermoelectric Coolers) directly atop heterogeneous packages to address active cooling for high-power AI chiplets.

Insight: For AI GPUs/ASICs, the bottleneck is no longer just the transistor, but “I/O Bandwidth + Heat Dissipation + Mechanical Reliability.” TSMC’s patents show they aren’t just building more CoWoS lines; they are turning packaging, thermal modules, and mechanical design into a combined “technical moat.” This aligns with the high CapEx allocated to AI advanced packaging.

3. High Capex & Gross Margin Goals → Equipment/Process Control Patents are Key

● Earnings Call Summary: TSMC set a 2026 gross margin target of 63–65%, with a long-term goal of remaining above 56% throughout cycles, despite the 2-4 percentage point dilution from the initial N2 ramp-up and overseas fab costs.

● Patent Trends: Significant investment in “Process Efficiency and Uniformity”:

o Hybrid Lithography Systems: Combining traditional reduction exposure with direct-beam writing to optimize different regional densities, increasing throughput and lowering costs without sacrificing critical pattern quality.

o Tunable PEZ (Plasma Exclusion Zone): Using adjustable rings to control plasma distribution, improving uniformity between the wafer edge and center, which directly impacts yield.

o Highly Adjustable Wafer Supports/Chucks: Fine-tuning the distance between the wafer and the process head to ensure more stable deposition/etching/exposure conditions, thereby reducing defects.

o ALD Precursor Recycling & Detection: Systems to increase material utilization and lower the unit cost per process step.

Insight: To defend high margins amidst massive Capex and the costs of overseas expansion/N2 ramp-up, TSMC relies on more than just pricing. They use “Equipment and Process Control” patents to push the cost and yield of every single wafer to the limit, echoing management’s confidence in their margin targets.

Share

4. N3/N2/N2P Roadmap → Extending into BEOL/3D/Thermal Management

● Earnings Call Highlights:

o N3 gross margin will exceed the corporate average within 2026, becoming the mainstay for AI/HPC.

o N2 mass production has begun; N2P and A16 are on the way, emphasizing new architectures such as backside power delivery networks for logic.

● Patent Presentation:

o BEOL Logic: Implementing BEOL‑compatible logic elements together with specialized interconnect structures in the BEOL stack, enabling additional logic capacity above the FEOL and supporting finer-grained 3D partitioning

o TSV Optimization: Improving guard rings and metal layouts around TSVs to reduce parasitic effects and noise coupling, clearly preparing for higher signal integrity in 3D chip stacking.

o Thermal Paths: Designs for internal thermal paths using tailored cavities, high-conductivity materials, TEC integration, and mechanical stress reinforcement to handle the thermal limits of high-power-density AI chips.

Insight: TSMC does not view “N2 → A16” as just a nanometer figure. It is an entire platform combining BEOL-compatible logic, 3D-IC, advanced packaging, and co-designed thermal management solutions. Future product differentiation will depend on total system performance, performance per watt, and bandwidth, rather than just the nominal logic node.

Strategic Inferences

Packaging as the “Second Main Battlefield”

With Capex reaching $52–56 billion in 2026 (10-20% for packaging/testing/mask) and CoWoS capacity doubling to 125k–130k wafers/month by late 2026, TSMC is elevating advanced packaging from a “back-end support role” to a strategic level equal to wafer fabrication. The goal is to use CoWoS/SoIC/InFO combined with HBM/Chiplets as the solution to AI/HPC bottlenecks.

Global Capacity: Overseas Fabs Bound to High-End Packaging

TSMC isn’t just building wafer fabs in Arizona; they are planning CoWoS/SoIC packaging lines there (2026–2029) to serve products like NVIDIA Rubin and AMD MI400. Overseas expansion is not just “capacity replication” but a “High-End Logic + High-End Packaging” pair, allowing for the full AI GPU/ASIC flow to be completed locally.

Conclusion

TSMC is upgrading its positioning from a “leader in advanced process nodes” to a “critical infrastructure provider for the AI/HPC era.”

1. Long-term Structural Demand: Focused investment in N2/N2P/A16 and 3D/BEOL structures targets a decade of AI demand.

2. System-Level Moat: Shifting competition from single-node advantages to “Integrated System Platforms” (Logic + 3D + Packaging + Thermal).

3. Financial Resilience: Using equipment and process control patents to create a “cost and yield moat” that maintains ~60% gross margins and high ROE.

Editor’s Note: The IP Insights Series is a collaborative initiative between Deeli AI, Mission International Patent & Trademark Office, and TechSoda, powered by the Deeli AI platform to analyze patents and papers.

Subscribe now

C. C. Wei, chairman of the world’s largest semiconductor foundry manufacturer, Taiwan Semiconductor Manufacturing Corp (TSMC), said at the fourth-quarter 2025 earnings call that the company’s biggest headache is not a bubble, but having to bridge the gap between customer demand and its available supply of advanced semiconductor chips.

TSMC again reported a stellar earnings report that surpassed previous guidance and market expectations, thanks to the insatiable demand for AI computing power. Yet, throughout the earnings call, all the executives talked about was that they have to work hard to meet customers’ demand and win their trust.

“The capacity is very tight. We work very hard to narrow the gap (between demand and supply). Probably this year, next year, we have to work extremely hard to narrow the gap,” said Wei, confirming that TSMC has purchased another plot of land in Arizona for fab expansion.

Earlier today, OpenAI announced that it will purchase up to 750 megawatts of computing power over three years from chipmaker Cerebras. Andrew Lu, a senior semiconductor industry analyst based in Taipei, estimates that the deal is likely to create a US$10-14 billion system-on-wafer value. Since Cerebras is a customer of TSMC, that will also contribute to its revenues.

The foundry giant has already committed US$165 billion to make advanced chips in Arizona, and is reportedly planning to build five more fabs beside the ones in operation or currently in the process of construction.

“With our strong technology leadership and differentiation, we are well positioned to capture the multi-year structural demand from the industry, mega trends of 5G, AI, and HPC in 2025,” said TSMC CFO Wendell Huang. “In 2026, we expect our capital budget to be between US$52-56 billion. Our level of capital spending is in anticipation of the growth that will follow in the future years.”

TSMC’s capital expenditure in 2025 totaled US$40.9 billion, compared to US$29.8 billion in 2024. That translates into around 37% growth for the third year in a row. Huang also revealed that TSMC’s capex totaled US$167 billion over the past five years, while R&D investment totaled US$30 billion, to maintain its lead in the capital-intensive industry.

When asked whether TSMC could significantly increase capital expenditures again—potentially to around US$200 billion over the next three years—given even stronger demand than in the past, Huang clarifies that while capex has already stepped up meaningfully, there is an inherent lag: it takes two to three years for new fab investments to translate into production capacity.

As a result, 2026–2027 will be more focused on productivity improvements, while capacity added from current investments will mainly come online in 2028–2029. TSMC reiterates that the capex being spent today is intended to support future output, and that capex in the next three years will be significantly higher than in the previous three years, though no specific multi-year dollar figure is formally committed.

Share

C.C. Wei acknowledges that TSMC is aware of the high risk of its US$52–56 billion capital spending and has been cautious by extensively verifying customer demand, including demand from cloud service providers (CSPs) and their end customers. After reviewing concrete business results and financial strength—especially among AI-driven hyperscalers—the company is confident that AI is delivering real, measurable value and driving sustained growth. TSMC is also benefiting internally from AI through productivity gains that help support margins despite high costs.

Overall, management views AI as a long-term, “mega” trend that is increasingly embedded in daily life and likely to support strong semiconductor demand for years. By maintaining leadership in fundamental technology, manufacturing excellence, and customer trust, TSMC expects solid long-term growth, targeting around a 25% compound annual growth rate (CAGR), while projecting AI’s CAGR to be more than 50% between 2024 and 2029. To meet surging AI demand—largely from U.S.-based customers—TSMC is accelerating capacity expansion in both Taiwan and Arizona, with U.S. fab performance approaching Taiwan levels and progress supported by government assistance.

Is Electricity the Reason for Aggressive Arizona Expansion?

However, Taiwan’s power supply shortage is a big challenge that may prevent TSMC from achieving its goals.

C.C. Wei admits that TSMC is concerned about securing sufficient electricity in Taiwan to support unrestricted capacity expansion and the growth of AI data centers.

Globally—especially in the U.S.—TSMC has also reviewed the readiness of the broader ecosystem, including power generation (such as turbines and nuclear plants), racks, and cooling systems, and finds conditions generally adequate. As a result, TSMC’s key challenge is to work aggressively to close the gap between surging AI-driven demand and its own manufacturing supply capacity.

Wei said his major CSP customers told him they had anticipated power needs five to six years in advance and had already addressed power supply planning. From their perspective, the main bottleneck is now semiconductor supply from TSMC, not electricity or infrastructure.

In other words, even though manufacturing cost in Arizona is much higher than that of Taiwan, since Taiwan’s power supply is unlikely to be resolved in the next five-to-six years, it makes perfect sense for TSMC to accelerate fab expansion full steam in Arizona.

Price Hikes Likely to Continue

Now, expect price hikes to be the norm.

When an analyst asked whether TSMC’s recent ~20% blended wafer ASP increase—driven by a higher mix of leading-edge nodes and price adjustments—represents a new normal, management hinted yes, but explained that while each new process node comes with higher pricing and this trend is likely to continue, pricing alone is not the main driver of profitability.

Wendell Huang told the analyst that price increases have largely offset inflation in tools, equipment, materials, and labor in recent years rather than significantly expanding margins. “TSMC’s sustained profitability instead comes from multiple factors: high utilization rates supported by strong demand and disciplined capacity planning, ongoing manufacturing excellence and productivity improvements, and flexible capacity optimization across nodes (including conversions from N5 to N3 and cross-node support),” said Huang. “Together, these enable TSMC to maintain healthy, sustainable returns while continuing to invest to support customer growth.”

Subscribe now

Competitors Rolling Up Sleeves for 2nm and Below

TSMC expects its 2-nanometer process to see a fast ramp in 2026, with very strong customer interest and demand. Huang notes that 2nm will be a larger node than 3nm from the outset in absolute revenue dollars, but that its percentage contribution to total revenue is now less meaningful given TSMC’s much larger overall revenue base.

Read more

As of the close of trading on December 31, 2025, Nvidia became the first company in history to maintain a US$5.03 trillion market capitalization. The speed of this ascent—climbing from $4 trillion to $5 trillion in just 79 days—has left analysts debating whether we are witnessing a repeat of the 1929 bubble or the dawn of a new industrial revolution.

What was the market cheering for? Beyond the raw numbers, the catalyst was Nvidia’s announcement of a US$20 billion deal involving Groq.

It suggests that the "Great Build-out" phase of massive cloud infrastructure is evolving. The focus is shifting toward the "Edge"—where speed, efficiency, and real-time application meet the physical world.

1. The Trillion-Dollar Question: Bubble or Revolution?

The total amount of AI infrastructure investments reached US$2.3 trillion as of the end of December 2025, and another US$3.9 trillion is waiting to be built in the next few years.

The US$910 billion investment during the Internet and telecom bubble in the late 1990s and early 2000s was insignificant in comparison.

Just like previous experiences, some say artificial intelligence is over-hyped, and some say we are just at the beginning of another industrial revolution. The Internet-driven dotcom bubble burst in the early 2000s was a painful memory for some people, and thus, whether profits can justify current and future AI investments became the center of debates.

A Bloomberg report writes that every firm on Wall Street is well aware of the risks surrounding the artificial intelligence boom. But across the investment outlooks from more than 60 institutions compiled here by Bloomberg News, the optimism for AI is almost universal.

Few would deny the possibility that when AI triggers a new industrial revolution, infrastructure investments are essential and will significantly accelerate a paradigm shift and productivity leap, just like the first, second, and third industrial revolutions.

It is a consensus in retrospect that the three industrial revolutions over the past – engines, electricity, telecom, and the internet – have significantly boosted the productivity of mankind. However, data provided by French economist Thomas Piketty showed that during the time of the industrial revolution, such as the locomotives and railroad buildouts in the 19^th century, the CAGR in GDP in England was only 3.3%, and in North America and Western Europe was less than 2%. It takes 40-50 years for the new technology’s contribution to be reflected in the gross domestic product (GDP) numbers, observes Roger Chen, a software industry research analyst.

“However, it would be a hyperbole to say AI is an industrial revolution that will last 100 years,” Chen said. “However, history tells us that when the underlying technology goes through a paradigm shift, new market leaders will emerge.” Chen draws insights from various research and concludes that AI is more of a 20-year iteration, with boom-and-bust cycles.

An IMF analysis shows that in the US, AI-producing sectors’ value added quadrupled from $278 billion (in constant 2017 dollars) to $1.13 trillion between 2010 and 2023, a rate much faster than that for private nonfarm and manufacturing value added. As a result, these sectors’ share in total US GDP increased from 2.4% in 2013 to 3.5% in 2023, with the data-processing sector nearly doubling its share in the same period. This fast growth of AI-producing sectors was driven by remarkable gains in labor productivity, with value added per employee in the data-processing sector.

Meanwhile, the share of manufacturing declined by 1.5 percentage points—further evidence of a K-shaped economy marked by widening wealth inequality, a pattern that is also increasingly evident in Taiwan.

Unpacking the current AI infrastructure value chain, Graphic Processing Units (GPUs) and NVSwitch accounted for 72% of the profits, while other components, such as the Central Processing Units (CPUs+memory+network interface cards, etc.), took away 12%.

Although optimistic estimates about trillion-dollar markets for AI are circulating, doubts about the widening gap between investment inputs and economic output have turned many investors’ cold feet. That had resulted in some market volatility in the fall of 2025, when several multi-billion-dollar deals investing in OpenAI were announced one after another.

Jack Chang, a securities researcher, pointed out that although debt financing of AI infrastructure shot up to US$126 billion in 2025, up 641% from 2024, it only accounted for 5% of the investment-grade bonds issued by US companies. Asset-backed securities (ABS) increased by 65% year-over-year to around US$30 billion in 2025.

“The corporate debt side related to AI totaled US$334 billion as of December 2025,” said Chang, citing research data by Bank of America. “Which is still at a safe level for now.”

However, data from Cushman & Wakefield showed that there are 42GW of computing power currently in operation, but there are 12GW that are under construction and another 66GW planned to be constructed in the next 10 years. Since building 1GW capacity of an AI datacenter can cost tens of billions of dollars when accounting for land, power, construction, cooling, networking, and GPU systems, just imagine how much more capital will be needed for those ambitious projects.

That matches the prediction of Nvidia CEO Jensen Huang, who predicted that the world will see dozens of GW AI factories in the next decade. At the 2025 GTC Keynote in Taiwan, he stressed that AI factories are not “smart factories” for manufacturing hardware, but computational infrastructures specifically designed to provide the computational power required for AI.

Subscribe now

2. From Cloud to Edge

One thing is certain – while pre-training and post-training continue in the cloud, computing and inferencing at the edge are gaining momentum.

Groq’s Language Processing Unit (LPU) technology is optimized for low-latency AI inference. It is built for ultra-fast, deterministic computing -- ideal for real-time inference across large-scale. The US$20 billion acquisition includes licensing Groq’s inference tech and hiring top talent like founder Jonathan Ross, bolstering Nvidia’s position amid rising competition in AI hardware.

Inference chips require lower latency, higher throughput, and better energy efficiency, especially when the computing happens at the edge. The most important part of Nvidia’s acquisition is technology licensing and talent. This is a move to bolster Nvidia’s stack and retain talent. It would represent a strategic setback for Nvidia if Groq’s elite talent were to defect to competitors such as Microsoft, Google, Meta, or AWS—companies that are already accelerating efforts to build proprietary chips.

When connected autonomous cars and the environment mature, edge computing and inference would be the core technology to enable the application. Although some challenges still need to be addressed for safety concerns, experts said autonomous and connected vehicles are no longer a distant promise.

A recent research report on robotaxis by senior technology analyst Andrew Lu suggests that the robotaxi business could become a far more powerful revenue engine for Tesla than its traditional vehicle sales. If that’s the case, why wouldn’t the same logic apply to other companies capable of developing comparable autonomous driving technologies? And could this be part of what Jensen Huang has in mind—accelerating Nvidia’s decision to acquire Groq to strengthen its position in this emerging market? To what extent does Groq’s IP enable Nvidia to pair GPUs with LPUs for hybrid edge systems, reducing latency and energy costs?

3. When the big gets bigger –

Readers may have noticed that Nvidia’s US$20 billion acquisition of Groq was structured not as a full merger but as a non-exclusive licensing arrangement for Groq’s inference technology, allowing Groq to continue operating independently.

“This sets a precedent for what could be seen as an informal acquisition, potentially reducing the risk of government intervention or antitrust scrutiny,” said Alan Chen, Head of Growth at Deeli AI, an AI-native platform for technology scouting and assessment. “Going forward, large companies may increasingly opt to license core technologies or quietly absorb key talent from startups whose innovations pose a competitive threat.”

“That would be unfortunate for the startup ecosystem,” Chen added. “The giants would continue to grow larger, while innovative startups struggle to scale beyond a certain point and choose to be acquired instead.”

Still, technology exploration and new ideas always come from lean and agile organizations. Startups remain an important engine of innovation.

More innovative applications are needed to leverage data center resources and translate raw compute power into real economic value. Dr. Jenher Jeng, founder and Chief Scientist of EdgeCrux—a startup applying AI to knowledge management and productivity tools for enterprise AI transformation—emphasized that as AI continues to evolve, integrated and sustained innovations in services and products will be essential to generate demand for AI computing resources.

4. Do we have enough energy for AI?

That being said, innovative AI solutions are needed more than ever to bolster the demand for AI infrastructure and computing capacities. However, when AI becomes ubiquitous, it is essential to make electricity cheap enough to sustain the operations.

However, cheapness comes with abundance. The question is, do we have enough energy to provide cheap electricity for AI?

Besides renewable energies, data centers are now embracing nuclear and small modular reactors, while innovative ideas of moving data centers to space or orbiting satellites are getting attention recently.

5. Circular Energy as an Option

Power-hungry data centers also require extensive cooling, resulting in enormous water consumption. In response, some creative approaches have emerged, such as redesigning data center “spas” that reuse waste heat or capturing excess heat for secondary power generation.

The idea of harvesting energy from vehicles—the principle that gave rise to hybrid cars—could offer another source of inspiration. If autonomous vehicles represent the future of mobility, why not enable them to sell excess electricity generated during operation back to the grid when they return for maintenance or routine checkups at the end of the day?

The Dawn of the “Inference Economy” (AI-driven Economy based on the IoT)

Where is AI heading? We are entering the era of AI ubiquity. The Nvidia-Groq deal signals that the battleground has moved from the cold halls of the data center to the “living edge”—the cars we drive, the robots that assist us, and the devices in our pockets.

The massive valuations we see today are a bet that AI will not just be a software upgrade, but the new “electricity” for the 21st century. However, the path forward is not a straight line up. As we navigate the “K-shaped” risks of wealth inequality and the looming energy crisis, the winners will not necessarily be those with the most data, but those who can monetize that data with the least amount of power and the lowest amount of latency.

The $5 trillion milestone is a testament to the hardware that built the foundation. The next $5 trillion, however, will be won by those who can make AI invisible, efficient, and integrated into the very fabric of our physical reality. We are no longer just building a brain; we are building the nervous system for a new global economy.

Share

Editor’s Note: Thank you for supporting TechSoda’s quality content. This article will be free for a week.

Taiwan’s integrated circuit (IC) industry maintained strong growth in the third quarter of 2025, continuing to ride the wave of global semiconductor recovery driven by AI infrastructure demand, high-performance computing, and a gradual rebound in consumer electronics. According to the Taiwan Semiconductor Industry Association (TSIA), total IC industry revenue — encompassing design, manufacturing, packaging, and testing — reached NT$1,669.7 billion (US$52.0 billion), marking a 4.4% increase from the previous quarter and a 20.6% rise year-on-year.

Globally, semiconductor revenue reached US$208.4 billion in Q3 2025, up 15.8% quarter-on-quarter and 25.1% year-on-year, according to World Semiconductor Trade Statistics (WSTS). The industry also saw a 6.9% increase in sales volume and an 8.4% rise in average selling price (ASP), reaching US$0.735 per IC. This combination of higher shipment volume and improved pricing signals a broad-based upturn across multiple segments — from memory and logic to analog and power devices.

Global Momentum Anchored in the U.S. and Asia-Pacific

Regional performance data from WSTS reflects diverging growth patterns. The United States led the surge, with semiconductor revenue climbing 22.2% on-quarter and 30.6% year-on-year, propelled by investments in AI accelerators, cloud infrastructure, and automotive electronics. Asia-Pacific (excluding China) followed closely with a 19.2% quarterly gain and an impressive 47.9% annual increase, underscoring the strength of foundry services and fabless design clusters in Taiwan, South Korea, and Southeast Asia.

Meanwhile, China’s semiconductor market grew 10.2% on-quarter and 15.0% year-on-year, reflecting ongoing efforts to localize chip supply chains despite export restrictions. In contrast, Japan and Europe exhibited slower momentum, with Japan’s quarterly growth of 5.2% overshadowed by a 10.2% annual decline, as legacy node demand softened.

Note:

· IC Industry Revenue = IC design + Manufacturing + Packaging + Testing

· IC Production Revenue = IC Design + Memory and other manufacturing products

· IC Manufacturing Revenue = Foundry + Memory and other manufacturing products

· Only companies headquartered in Taiwan are included in this report.

Subscribe now

Taiwan: Foundry-Driven Growth and Diversification

TSIA’s data shows that Taiwan’s IC manufacturing sector — led by foundries — remains the nation’s dominant growth engine. Q3 manufacturing revenue surged 6.4% quarter-on-quarter and 26.8% year-on-year, reaching NT$1,137.2 billion (US$35.4 billion). Foundries contributed NT$1,080.6 billion (US$33.7 billion) of that total, marking 5.7% quarterly and 27.0% annual growth.

“Taiwan’s foundry segment continues to benefit from global demand for advanced process nodes, particularly in AI and high-performance computing applications,” said a TSIA analyst familiar with the report. “Despite persistent supply tightness in advanced packaging and lithography equipment, utilization rates across major foundries remained above 90%.”

The memory and other manufacturing segment, which had been depressed for most of 2023 due to pricing pressure, showed signs of stabilization. Revenue rebounded 21.2% on-quarter and 23.9% year-on-year to NT$56.6 billion (US$1.8 billion), thanks to modest price recovery in DRAM and NAND markets. The memory and other manufacturing segment anticipates another 49.7% YoY growth in Q4.

Design Sector Sees a Pause Amid Inventory Normalization

In contrast, Taiwan’s IC design industry — the world’s second largest after the U.S. — experienced a mild pullback in Q3. Revenue stood at NT$349.0 billion (US$10.9 billion), down 2.9% from Q2, though still up 7.2% year-on-year.

Analysts attribute the quarterly dip to ongoing inventory adjustments, particularly in consumer, networking, and automotive segments. “Design houses are transitioning from a period of aggressive restocking earlier this year to a more balanced inventory posture,” noted the report. “However, mid- to long-term fundamentals remain positive, supported by demand for AI accelerators, automotive MCUs, and edge-computing chips.”

Steady Gains in Packaging and Testing Reflect Backend Strength

The backend sectors — packaging and testing — continued to post healthy growth.
Packaging revenue reached NT$125.2 billion (US$3.9 billion), an 8.4% increase on-quarter and 12.4% on-year, driven by demand for advanced system-in-package (SiP) solutions and 2.5D/3D integration used in AI chips and smartphones.
Testing revenue climbed to NT$58.3 billion (US$1.8 billion), up 4.5% on-quarter and 15.4% year-on-year, buoyed by strong utilization at leading outsourced semiconductor assembly and test (OSAT) providers.

TSIA noted that the backend industry has become a key beneficiary of heterogeneous integration trends, as major foundries expand their in-house packaging capabilities while relying on domestic OSAT firms for volume production.

Full-Year Outlook: 22% Growth in 2025

Looking ahead, TSIA forecasts that Taiwan’s total IC industry revenue will reach NT$6,482.5 billion (US$201.9 billion) in 2025, representing a 22.0% annual increase from 2024. The manufacturing segment is expected to post 26.9% growth, while design, packaging, and testing are projected to grow 12.6%, 13.9%, and 14.0%, respectively.

Within manufacturing, foundries are forecast to expand 27.5%, outpacing the 16.1% growth expected in memory and other manufacturing products. The sustained double-digit momentum suggests that Taiwan’s semiconductor ecosystem remains resilient amid global realignments in supply chains and technology sovereignty policies.

Globally, WSTS projects total semiconductor revenue to hit US$727.7 billion in 2025, up 15.4% from 2024 — indicating that Taiwan’s performance will continue to outpace the worldwide average.

Analysis: Strategic Positioning and Emerging Risks

The 2025 rebound marks the second consecutive year of double-digit growth for Taiwan’s IC industry, following a 22.4% expansion in 2024. The data points to a maturing recovery that is broad-based but still heavily reliant on high-end foundry output.

Read more

The company is achieving this not only by providing resilient, multi-orbit technology but also by embedding itself directly within Taiwan’s dynamic and innovative R&D ecosystem.

Dr. Vagan Shakhgildian, President of Comtech Satellite Network Technologies Corp, outlined the company’s comprehensive strategy in a recent interview with TechSoda on the eve of the Asia Pacific Space Community Council (APSCC) Satellite Conference 2025, with the theme of “Sovereignty and AI”, held in Taipei for the first time. “At this point, the ecosystem is actually more important than the supply chain,” said Shakhgildian. “Our collaboration with TMYTEK is a prime example of us doing that.”

TMYTEK is an electronic scanning antenna (ESA) solution provider based in Taiwan.

At this year’s Satellite 2025 exhibition in Washington D.C., Comtech and TYMTEK unveiled a “Multi-Orbit Satellite Resilient Network Solution,” offering more efficient connectivity options for global mobile network operators (MNOs), enterprises, governments, and specialized applications.

Shakhgildian saw that Taiwan is very much a part of the vibrant Asia-Pacific region, which is undergoing an enormous transformation. “And that’s what gives us confidence that this innovative ecosystem that you’re developing in Taiwan is not just a blip…. Across the region, you have many customers that fuel the demand for technology innovation from emerging economies to established technology hubs as the digital acceleration across the region is truly reshaping industries, communities, and governments.”

He emphasized that Comtech brings decades of experience, expertise, and a successful track record in providing interference-resilient solutions to the US government and various allied governments—including the Taiwanese government—across the globe. This background provides a crucial foundation for addressing Taiwan’s unique resilience needs in the Asia-Pacific region.

The Multi-Orbit Answer to Blockade Fears

For Taiwan, the primary challenge for communication resilience is maintaining seamless connectivity even in the event of natural disasters or a potential geopolitical blockade that could sever its critical undersea fiber-optic links. As Dr. Shakhgildian acknowledges, while adversaries may seek to interfere with traditional communications, satellites themselves are not immune to jamming or bad actors. Therefore, he stresses that the ultimate and most resilient solution lies in the “plurality of solutions” offered by multi-orbit satellite capabilities.

Comtech’s modern approach provides inherent resilience by ensuring communication pathways can be dynamically switched across different satellite constellations:

1. Geostationary Earth Orbit (GEO): Traditional, high-altitude satellites providing wide coverage.

2. Medium Earth Orbit (MEO): Mid-altitude satellites offering lower latency and better throughput.

3. Low Earth Orbit (LEO): Newer, fast-moving satellites promising the lowest latency and highest bandwidth for demanding applications.

A cornerstone of this solution is Elevate 2.0, Comtech’s innovative, next-generation, cloud-native platform. This fully software-defined system is specifically designed to enable network operators and service providers to automatically and dynamically select the optimal connectivity path across GEO, MEO, or LEO, ensuring that communication flows freely and efficiently based on each application’s specific performance needs.

Furthermore, Comtech highlighted the resilience of its hardware. The company’s SLM-5650B modem, widely used by the U.S. and allied governments, is the first “sovereign” certified modem to operate on the SES O3b mPOWER constellation. This certification is critical, as it demonstrates that existing, proven hardware can be seamlessly adapted for multi-orbit connectivity, a key feature in modernizing ground segment equipment. Comtech’s expertise, Shakhgildian noted, is predominantly active in the ground segment—manufacturing equipment for Earth stations—but also extends to space-qualified components and intellectual property for signal processing units.

Collaboration Fuels Innovation Over Supply Chain

Comtech views its presence in Taiwan as more than just a business transaction; it is a collaborative R&D partnership. The company’s Canadian subsidiary, Comtech Satellite Network Technologies Corp, is actively engaged in a joint project with Taiwanese partner TMYTEK (TMY Technology Inc.) under the framework of the Eureka consortium, a Canada-Taiwan collaboration program that operates under the auspices of the European Union, the Canadian Space Agency, and others.

Eureka is the world’s largest intergovernmental network of countries supporting international research, development, and innovation. Founded in 1985 by 18 countries and the European Commission, Eureka has since grown beyond these geographic borders, spanning 47 countries, including Taiwan and Canada.

This high-level partnership is focused on developing state-of-the-art, software-defined SATCOM terminals. The long-term goal is to produce a super compact satellite terminal equipped with an electronically steerable antenna. This project leverages TMYTEK’s expertise in digital RF beamforming, a capability that extends beyond SATCOM and into advanced 5G cellular systems.

Shakhgildian emphasized that this focus on innovation is more important than the traditional hardware-oriented supply chain. He views this strategic collaboration as a prime example of Comtech engaging with Taiwan’s innovative core, rather than just its manufacturing capacity. The regional dynamism, driven by digital acceleration across the Asia-Pacific, provides the sustained demand that validates and fuels this innovation ecosystem.

Beyond 5G: The Path to 6G and Future Cooperation

Looking ahead, Comtech believes the convergence of satellite and terrestrial communications will deepen significantly with 6G technology. Shakhgildian points out that 5G already has a strong Non-Terrestrial Network (NTN) component, primarily composed of satellite connectivity. In 6G, the non-terrestrial component is expected to play an even bigger role, further cementing the strategic importance of satellite solutions for national connectivity.

The company confirms it is actively seeking new frameworks for collaboration and is currently in discussions with multiple major Taiwanese organizations with shared common values and geopolitical alignment between Canada and Taiwan.

By bringing decades of government-grade security expertise and cutting-edge multi-orbit platforms like Elevate 2.0, while simultaneously investing in Taiwanese R&D capabilities, Comtech is set to play an increasingly vital role in solidifying Taiwan’s standing as a highly resilient and connected technology hub.

This collaborative spirit, fueled by innovative technology, directly addresses the practical demand for reliable and flexible connectivity that is crucial to the island’s future.

The rumor that Intel is aggressively courting Dr Wei-Jen Lo —former Senior Vice President at TSMC—to return to the US and take a leading role in advanced process R&D has become a hot topic in Taiwan’s semiconductor circles. But how credible is this speculation? Would a 75-year-old veteran truly be willing to take on such a demanding role? And, having just retired from TSMC in July, would he risk violating non-compete terms? These factors all cast uncertainty on the rumor.

Notably, Wccftech pointed out: “For now, this is currently a rumor, and no announcements have been made from either TSMC or Intel to validate the joining of Wei-Jen Lo, but it seems like Intel is pursuing a newer approach with the foundry division, which involves recruiting ‘key talent’ to help with the company’s chip-making ambitions.”

Even assuming Dr. Lo were interested, Intel would still face significant structural challenges.

Subscribe now

1. R&D Scope and Practical Limitations

If recruited, Dr. Lo’s focus would likely center on advanced manufacturing yield improvements rather than AI chip design, where Intel already has established teams. However, it is unlikely he would bring a large team with him. Without a trusted and capable team, can his expertise translate into rapid yield recovery? Intel’s 18A process roadmap still faces yield hurdles, and time is not on its side. According to reports, the yields of Intel’s 18A process were around 10% at the beginning, but it has since improved, reaching approximately 55% by July 2025.

2. Cultural and Organizational Fit

Dr. Lo is widely known for his strict, disciplined management style—a reflection of his military family upbringing. This approach suited TSMC’s Taiwan fabs, which emphasize efficiency, hierarchy, and execution. But would the same style work at Intel, particularly after the organizational strains seen at its Arizona fabs?
Moreover, Intel today is a more fragmented, politically layered organization compared with the operationally unified TSMC. The cultural gap is real—and non-trivial.

3. Talent Depth and “General Without Troops” Dilemma

Under two consecutive CEOs focused on restructuring, Intel has laid off tens of thousands of employees, and many senior engineers have taken early retirement. Although recent financials show signs of stabilization, yield improvement is ultimately a talent-density problem. TSMC treats yield improvement as an R&D issue, a dedication involving top talent working in three shifts. Can Dr. Lo replicate that model in Intel?
Hiring a celebrated general is symbolic—but without elite engineers to execute, the general may have limited battlefield impact.

4. The IDM Business Model Trust Issue

Intel’s integrated device manufacturer model makes external customers wary: competing on CPUs while simultaneously providing foundry services creates inherent conflict. Unless Intel separates and independently operates its foundry business, customer confidence—and large-scale orders—will remain difficult to secure.
Senior semiconductor analyst Andrew Lu notes that Intel’s foundry division currently loses over $2B per quarter. When—and how—Intel chooses to restructure or divest this “hot potato” will be critical. He seems to believe that the possibility of TSMC participating via a technology stake, while speculative, cannot be ruled out in a geopolitically reshuffled semiconductor landscape.

The Non-Compete Question

As a former Senior Vice President involved in strategy and leading advanced-node development from 7nm to 2nm, Dr. Lo carries a depth of confidential process know-how. TSMC’s non-compete clauses are especially stringent for executives at his level.

While some argue that, as a US citizen, he could legally challenge or bypass such restrictions, others believe his long-standing respect for founder Morris Chang and his health considerations make a return to Intel unlikely.
To date, neither Intel nor TSMC has confirmed the rumor.

Broader Industry Context

During TSMC’s most recent earnings call, Chairman C.C. Wei mentioned that TSMC is assisting a “North American customer” with the most advanced product and advanced packaging technology, and that Arizona Fab 2 production will accelerate due to strong demand.
This has prompted speculation on whether the collaboration involves manufacturing support, advanced node co-development, or even technical advisory arrangements involving retired leadership talent. None of these possibilities can be ruled out yet.

Meanwhile, the industry is watching to see whether Intel can:

• Deliver competitive next-generation CPUs and GPUs to regain share from AMD and ARM;

• Successfully advance data center architectures and AI PC initiatives; and

• Strengthen its manufacturing credibility fast enough to retain relevance in the AI era.

A single legendary engineer, no matter how respected, cannot solve systemic organizational, cultural, and talent-density challenges alone. Intel’s future hinges not only on technology roadmaps, but on deep structural reform and the rebuilding of trust among customers and engineers alike.

Share

Overview of the Price Surge

DDR4 memory prices have experienced a dramatic surge in recent weeks. According to multiple industry reports, spot market prices for DDR4 chips increased by about 50% in the second half of May 2025 alone, with 8GB modules rising from $1.75 to $2.73 (a 56% increase) and 16GB modules climbing 45%. Contract prices for manufacturers also jumped 22–25% for these chips over the same period. Analysts expect further increases of 10–20% in the third quarter of 2025.

Key Reasons Behind the Surge

1. Manufacturer Phase-Out of DDR4 Production

• Major DRAM manufacturers (Samsung, Micron, SK hynix) are rapidly winding down DDR4 production to focus on newer, higher-margin products like DDR5 and high-bandwidth memory (HBM).

• Samsung, for example, is scheduled to cease DDR4 production in early June 2025.

• The shrinking profitability of DDR4 has accelerated this strategic shift as demand migrates to advanced platforms.

2. End of Chinese Oversupply

• Previously, Chinese manufacturers (notably CXMT and Fujian Jinhua) flooded the market with low-priced DDR4, undercutting global competitors.

• Recently, the Chinese government instructed these firms to halt DDR4 production, ending the period of oversupply and abruptly tightening global supply.

3. Stockpiling Due to Trade Tensions and Tariffs

• US-China trade tensions and the threat of new tariffs, particularly those announced by President Trump in April 2025, have led to widespread stockpiling of DDR4 chips by tech companies.

• Even though a temporary exemption was granted, uncertainty around future tariffs drove companies to build up inventories, further straining supply and driving up prices.

4. Shift in Production Capacity to High-End Memory

• The AI boom has increased demand for high-bandwidth memory and advanced DRAM, causing manufacturers to reallocate capacity away from traditional DDR4 and LPDDR4.

• As a result, the bit output for PC and mobile DRAM has been limited, reducing available DDR4 supply.

5. Market Dynamics and Procurement Strategies

• Buyers believe that DRAM prices have bottomed out, prompting aggressive procurement to lock in lower costs before further increases6.

• This has led to a rare period of growth in the memory chip sector after a prolonged downturn.

Analysis and Outlook (Opportunities and Risks)

Subscribe now

Read more

TSMC will hold its shareholders’ meeting on June 3 and the Q2 earnings call on July 17. Due to recent exchange rate fluctuations affecting its revenue and gross margin, the market is closely watching the company’s next moves, particularly any changes in wafer foundry pricing. Several related news items today are worth noting:

TSMC's Arizona plant will reach full capacity soon.
All five major clients—Apple, AMD, Qualcomm, Broadcom, and NVIDIA—will have their chip orders manufactured at the Arizona fab this year. Apple remains the largest customer, while NVIDIA’s AI chips will be “Made in the USA” starting by year-end. The first fab of TSMC Arizona is producing 15,000 12-inch wafers per month now and will soon reach 24,000 units, meaning it will reach full capacity soon, according to Nobunaga Chai, senior semiconductor analyst and deputy managing director at Cloud Express.

The industry believes that strong U.S. government support for local manufacturing and geopolitical pressures for offshoring production will help TSMC accelerate the ramp-up of its U.S. fab, ushering in a new wave of growth.

At the same time, wafer pricing is rising in line with process upgrades.
TSMC’s 2nm process is about to enter mass production, with major players like MediaTek, Apple, Qualcomm, Fujitsu, and AMD already committed. Commercial Times and Liberty Times reported that developing a single 2nm chip costs up to USD 725 million, with foundry pricing per wafer reaching USD 30,000, and potentially up to USD 45,000 in the future for the 1.4 nm process. These high costs mean that only top-tier players can afford to compete in the 2nm space and at even more advanced nodes. ZDNet Korea predicts that it takes only four quarters for TSMC’s 2nm node process to run at full capacity.

Share

By the end of this year, TSMC’s 2nm monthly capacity is expected to reach 30,000 wafers.
In 2026, the number of new tape-outs for TSMC’s 2nm process is forecasted to be four times that of the 5nm node, making 2nm the core battleground for advanced processes. Beyond mobile applications, AI accelerators and cloud service providers (CSPs) are expected to adopt the 2nm process for in-house chip designs, including Google’s 8th-gen TPU, AWS’s Trainium 4, and Microsoft’s Maia 300.

The supply chain reveals that the 2nm process involves over 2,000 steps,
requiring extremely advanced process control and technological know-how. TSMC has already established an irreplaceable technical moat. Over the next five years, the AI accelerator segment is expected to grow at a CAGR of nearly 45%, providing strong revenue momentum for TSMC.

Meanwhile, for the China market, NVIDIA is developing a new AI chip, the B30, which are, according to rumors, Blackwell architecture chips that do not use HBM (high-bandwidth memory) or TSMC’s advanced packaging, priced around USD 6,500 to 8,000 per unit, as a response to U.S.-China tech restrictions. More than one million units are expected to be shipped within the year, according to The Information. It will be based on Nvidia's RTX Pro 6000D, a server-class graphics processor, and will utilize conventional GDDR7 memory, according to Reuters, citing two sources. And who will be manufacturing the 1 million units of B30 for NVIDIA? According to Wealth Express, TSMC will produce them.

Overall, TSMC is riding the wave of AI and advanced processes.
Not only does it maintain technological leadership, but its client base and capacity expansion are also progressing robustly, signaling a new phase of rapid growth in the coming years.

Morgan Stanley reaffirms its “Overweight” rating on TSMC,
emphasizing that TSMC remains its top pick among Greater China semiconductor stocks. The report highlights three key figures to watch:

1. 2026 CoWoS capacity plans: Expected to be announced in early July, this will be a key indicator for demand in cloud AI chips such as GPUs and ASICs.

2. AI GPU shipments: If NVIDIA ships 10,000 units of its NVL 72 server in Q3, it could ease inventory pressure for its Blackwell chips.

3. Guidance in the July 17 earnings call: Full-year USD revenue is expected to grow 25–30%, though a stronger New Taiwan Dollar may impact gross margins.

Morgan Stanley believes that of the original three major concerns—Intel’s joint venture and AI demand—two have largely subsided. If U.S.-China tariff issues remain under control, TSMC’s valuation could be revised upward, and wafer pricing at the U.S. fab may rise by more than 10% to offset cost increases.

Support TechSoda to support your success!

Subscribe now

TSMC (台積電) unveiled a sweeping vision for the future of semiconductors at its 2025 Taiwan Technology Symposium in Hsinchu, spotlighting transformative advancements across process technology, AI applications, packaging, and power management. With artificial intelligence reshaping industry landscapes, the world’s largest foundry positioned itself as a central enabler of this revolution.

AI as the Next Frontier: From Generative to Physical

TSMC Asia-Pacific business director Rui-yang Wan (萬睿洋) identified "Physical AI"—including humanoid robots and autonomous vehicles—as the next major wave following generative and agent-based AI. He projected that the global AI robot market value will exceed US$35 billion in 2030, and by 2030, one in ten cars will be autonomous.

Wan cited 2024 as a breakthrough year for AI, with Nobel Prizes awarded for innovations in machine learning and protein structure prediction. He emphasized AI's accelerating impact in fields ranging from cancer diagnostics to astronomy and geophysics.

Looking ahead, generative AI is expected to transform over 40% of daily work tasks by 2028, while agent-based AI could handle 15% of decision-making, including travel planning and personal scheduling.

TSMC forecasts a proliferation of physical AI with 1.3 billion AI robots globally by 2035, expanding to 4 billion by 2050—including 650 million humanoid robots. This trend will push AI from the cloud to the edge, requiring breakthroughs in chip performance, power efficiency, and miniaturization.

Share

Technological Milestones: A14, A16, and 2nm Advances

TSMC Co-COO Kevin Zhang (張曉強) outlined a roadmap of new process nodes:

• A14 (1.4nm): Planned for mass production in 2028, A14 will offer a 15% speed boost, 30% power reduction, and 20% greater logic density compared to N2. It introduces “NanoFlex Pro” for better performance and flexibility, and a version with Super Power Rail (SPR) backside power delivery is due in 2029.

• A16 (1.6nm): Tailored for data center AI and HPC, A16 with SPR will begin volume production in late 2026.

• N2 (2nm): Mass production starts in late 2025. Its initial adoption by AI customers is already double that of N5 in its first year.

• N3 (3nm): Now in its third year, N3’s capacity will grow 60% in 2025, with derivatives like N3E, N3P, and N3X supporting diverse needs from HPC to automotive chips.

Packaging and Integration: 3DFabric, SoW-X, and Beyond

TSMC detailed major packaging advances:

• SoIC (System on Integrated Chips) for 3D silicon stacking will enter volume production in 2025 for N3-on-N4 configurations.

• CoWoS (Chip-on-Wafer-on-Substrate): CoWoS-L with a 5.5x mask size launches in 2026; CoWoS with a record 9.5x mask size, integrating 12+ HBM stacks, is planned for 2027.

• SoW-X (System-on-Wafer): Offering 40x performance improvement over CoWoS, it mimics full server rack capabilities and is set for 2027 mass production.

Foundry Expansion and Regional Growth

TSMC announced plans to build 9 new fabs in 2025 alone—8 wafer fabs and 1 advanced packaging plant. Of these, 11 fabs are currently under construction in Taiwan across Hsinchu, Tainan, Taichung, and Kaohsiung.

Notably, Fab 25 in Taichung will begin construction by year-end and aims for 2028 production using technology beyond 2nm.

In 2024, TSMC's Asia-Pacific clients used over 1.8 million wafers for 2,400+ products, contributing 10% of revenue, with 300 new products entering mass production soon.

Share TechSoda

Sustainability and Energy Challenges

A central issue raised at the forum was AI's exploding power demands. Delta Electronics’ Power Systems General Manager, Chen Ying-Yuan (陳盈源), revealed AI chips now consume up to 1,200W—tripling in four years—with projections reaching 2,400W by 2026. A single server rack with 576 GPUs could consume 1 Megawatt, matching 10,000 homes.

Delta outlined six infrastructure innovations, including:

• Power Conditioning Systems (PCS) to flatten AI load spikes

• Liquid cooling systems using two-phase metal chambers

• Micro and containerized data centers for rapid deployment

• High-frequency power modules to shrink transformer sizes by 90%

Delta is proposing solutions like PCS (Power Conditioning System) dynamic load compensation modules, high-frequency power conversion modules, and Two-Phase Metal Chamber cooling technology to address these challenges.

Next-Gen Special Technologies

TSMC is also pushing forward in niche domains:

• Memory: RRAM (12nm certified for automotive) and MRAM (22nm in production, 16nm ready, 12nm in development).

• IoT & RF: N4C RF cuts power and area by 30% vs. N6RF+, supporting Wi-Fi 8 and advanced TWS audio. Expected in trial production by Q1 2026.

• Displays: 16HV FinFET platform for foldable OLED and AR glasses reduces DDIC power by 28%.

• Auto: ADAS moving from 12nm/8nm to 5nm/3nm nodes. New image sensors and high dynamic range technologies also unveiled.

Long-Term Outlook: Toward a $1 Trillion Industry

TSMC expects the global semiconductor market to hit $1 trillion by 2030, driven by:

• AI/HPC: 45%

• Smartphones: 25%

• Automotive: 15%

• IoT: 10%

The company projects that by 2025, wafer shipments for AI-related products will be 12 times those of 2021, and large-die chip shipments will increase 8-fold—posing yield management challenges TSMC says it’s uniquely equipped to handle.

Industry Voices: MediaTek Weighs In

MediaTek President and COO Joe Chen (陳冠州) noted that large language model (LLM) capabilities are doubling every 3.3 months. He expects AI-investment to reach US$1 trillion by 2029, and flagship mobile computing power doubling every two years.

He stressed the need for standardized AI-agent interfaces (MCP) and reaffirmed strong collaboration with TSMC on advanced processes and packaging.

Specialized Technologies and Manufacturing

TSMC is also developing specialized technologies. These include:

• HBM base dies

• Silicon photonics solutions

• Integrated voltage regulators (IVR)

• High-density embedded deep trench capacitors

• Display technologies like the 16HV FinFET high-voltage platform

To support the AI boom, TSMC is expanding production capacity. The company's wafer shipments for AI products in 2025 are projected to be 12 times those in 2021, with large-die product shipments expected to increase eightfold. Advanced packaging capacity is also growing rapidly, with SoIC capacity CAGR exceeding 100% and CoWoS capacity CAGR over 80% from 2022 to 2026. TSMC is building 9 new fabs in 2025, and FAB 25 is planned to begin construction at the end of this year, with production of next-gen beyond 2nm technology to start in 2028.

The company reiterates its commitment to global manufacturing consistency through its Global Manufacturing Management Platform, ensuring overseas fab yield rates match those in Taiwan.

Subscribe now